CHAPTER 12 - Timing with a Software Timer

SummaryThe execution of agent‐based simulations (ABSs) on hardware accelerator devices such as graphics processing units (GPUs) has been shown to offer great performance potentials. However, in heterogeneous hardware environments, it can become increasingly difficult to find viable partitions of the simulation and provide implementations for different hardware devices. To automate this process, we present OpenABLext, an extension to OpenABL, a model specification language for ABSs. By providing a device‐aware OpenCL backend, OpenABLext enables the co‐execution of ABS on heterogeneous hardware platforms consisting of central processing units, GPUs, and field programmable gate arrays (FPGAs). We present a novel online dispatching method that efficiently profiles partitions of the simulation during run‐time to optimize the hardware assignment while using the profiling results to advance the simulation itself. In addition, OpenABLext features automated conflict resolution based on user‐specified rules, supports graph‐based simulation spaces, and utilizes an efficient neighbor search algorithm. We show the improved performance of OpenABLext and demonstrate the potential of FPGAs in the context of ABS. We illustrate how co‐execution can be used to further lower execution times. OpenABLext can be seen as an enabler to tap the computing power of heterogeneous hardware platforms for ABS.

This paper presents a smart water management system using the microcontroller ZR16S08 as IoT solution, for water distribution support and losses prevention. The system operates through the smart monitoring of the water flow in pipes of the water distribution network, aiming to ensure quality of the water supply, knowing that water losses characterize one of the great problems in the world, as pipe holes may be open doors to water contaminants. As an alternative to circumvent this issue, a series of experiments were taken to create a network of sensors capable of monitoring water pipes in real time. Adopting criteria such as low consumption and low cost, the use the ZR16S08 microcontroller in the design of wireless sensor nodes that will be coupled in the water pipes was adopted. Complementing the system, a central processing unit, composed of a Raspberry Pi microcomputer, manages the traffic of the information collected by the sensor nodes and routes it to a web server. All data addressed by the central unit are available on-line by means of a supervisory platform. Considering the size of the sensor nodes, their power consumption, and regulatory issues, a link between the sensor nodes, operating at a frequency of 433 MHz, was defined. Preliminary results show the effectiveness of the proposed architecture for sensor nodes, allowing application for the monitoring of water and controlling losses.

Hardware-in-the-loop test benches are distributed computer systems including software, hardware and networking devices, which require strict real-time guarantees. To guarantee strict real-time of the simulator the performance needs to be evaluated. To evaluate the timing performance a discrete event simulation model is built up. The input modeling is based on measurements from the real system in a prototype phase. The results of the simulation model are validated with measurements from a prototype of the real system. The workload is increased until the streaming source becomes unstable, by either exceeding a certain limit of bytes or exceeding the number of parallel software processes running on the cores of the central processing unit. To evaluate the performance beyond these limits, the discrete event simulation model needs to be enriched by a scheduler and a hardware model. To provide real-time guarantees an analytical model needs to be built up.

A method has been developed for evaluating central processing unit (CPU) coverage by automatically injecting faults into actual CPU hardware while it is executing relevant test software. A special hardware test fixture is used which contains the CPU under evaluation, program and data memory, and a terminal interface. The test fixture is connected to a microcomputer controller and an in-circuit read only memory (ROM) emulator. The faults injected are stuck-at-1, stuck-at-0, and open on the appropriate integrated circuit pins, plus the altered state of every microprogram memory bit. The effect of each fault is determined by observing the status of the monitor. Data reduction is performed after each run on a separate host computer, and summary results are tabulated. N digital avionics systems the central processing unit (CPU) is obviously the dominant functional element, upon which many other elements are dependent in order to perform correctly related interface and control tasks. Normally, there are arrays of system monitors, in both hardware and software, which have an inherently overlapping capability to detect CPU malfunctions. The combined effectiveness of these monitors determines the total CPU fault coverage. However, since many of these monitors are themselves dependent upon CPU operation, there is a critical topdown relationship between the monitors which must be considered. In particular, a software monitor is of little subsequent value in the presence of a CPU fault unless one of the two following conditions is present. 1) It is actually executed, and it produces the planned fault detection results, and the fault detection is properly communicated to and acted upon by the ultimate hardware control elements in the system. 2) It causes fault detection elsewhere when it is not executed, and the fault detection is properly communicated to and acted upon by the ultimate hardware control elements in the system. In simplest terms, software monitors depend upon a rational CPU; that is, a CPU which is at least able to follow the normal program flow without making addressing or branching errors. If this is not the case, then how can one guarantee that the software monitor is executed? If it is possible to detect the fault of concern without executing the software monitor, then why is the monitor present? The point is that it is critically necessary to have a CPU monitoring scheme which establishes the minimum CPU fault coverage that is required to support all other monitoring activity. Such a monitoring scheme must straddle the hardware-software boundary so that external communication is absolutely guaranteed. In the simple terms introduced in the preceding, such a monitor must be able to detect all faults resulting in irrational CPU operation. In most modern digital avionic systems, the monitor which does these things is the so-called watchdog monitor (WDM) (or alternately the heartbeat or deadman timer monitor). The WDM usually operates in relation to the timer

This paper introduces the newly developed Infini- Band (IB) Management Queue capability, used by the Host Channel Adapter (HCA) to manage network task data flow dependancies, and progress the communications associated with such flows. These tasks include sends, receives, and the newly supported wait task, and are scheduled by the HCA based on a data dependency description provided by the user. This functionality is supported by the ConnectX-2 HCA, and provides the means for delegating collective communication management and progress to the HCA, also known as collective communication offload. This provides a means for overlapping collective communications managed by the HCA and computation on the Central Processing Unit (CPU), thus making it possible to reduce the impact of system noise on parallel applications using collective operations. This paper further describes how this new capability can be used to implement scalable Message Passing Interface (MPI) collective operations, describing the high level details of how this new capability is used to implement the MPI Barrier collective operation, focusing on the latency sensitive performance aspects of this new capability. This paper concludes with small scale bench- mark experiments comparing implementations of the barrier collective operation, using the new network offload capabilities, with established point-to-point based implementations of these same algorithms, which manage the data flow using the central processing unit. These early results demonstrate the promise this new capability provides to improve the scalability of high- performance applications using collective communications. The latency of the HCA based implementation of the barrier is similar to that of the best performing point-to-point based implementation managed by the central processing unit, starting to outperform these as the number of processes involved in the collective operation increases.

The reliability of transformer units and extending their life depend greatly on the degree of monitoring of their functional parameters with a view to determining the proper predictive maintenance measures, according to their interpretation. The achievements presented in this paper are the result of continuous upgrading which consisted in: increasing calculation accuracy, replacing the fixed point calculation by calculation in floating point, increasing calculation accuracy by replacing 10-byte CAN with 16-byte CAN, increasing the speed of acquisition-calculation by allocating the acquisition and calculation functions, increasing the sampling rate, increasing the speed and security of data transmission from the local monitoring system to the central processing unit by introducing the fiber optic support, increasing the data storage space on flash memory units and providing the possibility of monitoring system software configuration, depending on the monitored parameters and the reference specific elements of the application. The paper presents a compact embedded and local version with fiber optic support implementation within the circuits for processing the information in the field corresponding to the local monitoring equipment of transformer units. The presented version is of integrated equipment implemented for a power transformer monitoring system. The central unit is a single casting structure adapted for easy fastening on electric panels, overall dimensions approx. 280mm × 230mm × 100mm.

Vision-based navigation has become increasingly important in a variety of space applications for enhancing autonomy and dependability. Future missions, such as active debris removal for remediating the low Earth orbit environment, will rely on novel high-performance avionics to support advanced image processing algorithms with substantial workloads. However, when designing new avionics architectures, constraints relating to the use of electronics in space present great challenges, further exacerbated by the need for significantly faster processing compared to conventional space-grade central processing units. With the long-term goal of designing high-performance embedded computers for space, in this paper, an extended study and tradeoff analysis of a diverse set of computing platforms and architectures (i.e., central processing units, multicore digital signal processors, graphics processing units, and field-programmable gate arrays) are performed with radiation-hardened and commercial off-the-shelf technology. Overall, the study involves more than 30 devices and 10 benchmarks, which are selected after exploring the algorithms and specifications required for vision-based navigation. The present analysis combines literature survey and in-house development/testing to derive a sizable consistent picture of all possible solutions. Among others, the results show that certain 28 nm system-on-chip devices perform faster than space-grade and embedded central processing units by 1–3 orders of magnitude, while consuming less than 10 W. Field-programmable gate array platforms provide the highest performance per watt ratio.

Zilog extends … sometime

Massive connectivity for massive machine-type communications (mMTC) is key enabler for many 5G and Intternet-of-Things (IoT) applications. In mMTC scenarios, a large number of low-complexity, low-rate devices transmit sporadically over shared scarce communication resources. Reliability and low-latency with short packet transmissions are major design criteria that require integration of novel network architecture solutions and multiple access methods. This study addresses the challenge of massive connectivity in the context of a Cloud Radio Access Network (C-RAN), characterized by a hierarchical structure in which part of the processing functionalities of the Radio Units (RUs) are migrated to a centralized cloud processor or Central Unit (CU). A major architectural constraint of C-RANs is imposed by capacity-limited fronthaul links connecting the RUs with the CU. In this study, the performance of a transmission scheme for massive connectivity is investigated under this architectural constraint. In particular, a non-coherent, grant-free transmission scheme is proposed where the encoding is performed based on a Gabor frame structure. The fronthaul processing is a particular instance of Detect-and-Forward (DtF), where local detection at the RUs is performed using a one-step thresholding procedure, and the local estimates are then merged at the central processor via the capacity-limited fronthaul links. Numerical results illustrate the potential of the proposed scheme to support massive, reliable random access with short messages.

Microprogramming has traditionally been done in assembly language because of the perceived need for fast execution; compiler technology does not yet exist for discovering and performing many of the clever tricks of an experienced microprogrammer. Unfortunately, programming at the machine-instruction level is both tedious and error-prone. A possible compromise between these two approaches is that of an interactive compiler, where the programmer guides the crafting of critical data structures and sections of code, while the compiler ensures that the resulting code has the same semantics as the original program, generates code where speed is not critical, and performs bookkeeping tasks. We are in the process of implementing a prototype of such a system. This paper describes the system being developed and discusses some of the key design issues.

Microprogramming has traditionally been done in assembly language because of the perceived need for fast execution; compiler technology does not yet exist for discovering and performing many of the clever tricks of an experienced microprogrammer. Unfortunately, programming at the machine-instruction level is both tedious and error-prone. A possible compromise between these two approaches is that of an interactive compiler, where the programmer guides the crafting of critical data structures and sections of code, while the compiler ensures that the resulting code has the same semantics as the original program, generates code where speed is not critical, and performs bookkeeping tasks. We are in the process of implementing a prototype of such a system. This paper describes the system being developed and discusses some of the key design issues.

Soluble solid content (SSC) is a major quality parameter to fruit, which has influence on its flavor or texture. Some researches on the on-line non-invasion detection of fruit quality were published. However, consumers desire portable devices currently. This study aimed to develop a portable device for accurate, real-time and nondestructive determination of quality factors of fruit based on diffuse reflectance Vis/NIR spectroscopy (520-950 nm). The hardware of the device consisted of four units: light source unit, spectral acquisition unit, central processing unit, display unit. Halogen lamp was chosen as light source. When working, its hand-held probe was in contact with the surface of fruit samples thus forming dark environment to shield the interferential light outside. Diffuse reflectance light was collected and measured by spectrometer (USB4000). ARM (Advanced RISC Machines), as central processing unit, controlled all parts in device and analyzed spectral data. Liquid Crystal Display (LCD) touch screen was used to interface with users. To validate its reliability and stability, 63 apples were tested in experiment, 47 of which were chosen as calibration set, while others as prediction set. Their SSC reference values were measured by refractometer. At the same time, samples' spectral data acquired by portable device were processed by standard normalized variables (SNV) and Savitzky-Golay filter (S-G) to eliminate the spectra noise. Then partial least squares regression (PLSR) was applied to build prediction models, and the best predictions results was achieved with correlation coefficient (r) of 0.855 and standard error of 0.6033° Brix. The results demonstrated that this device was feasible to quantitatively analyze soluble solid content of apple.

This study examines vectorized programming for finite impulse response image filtering. Finite impulse response image filtering occupies a fundamental place in image processing, and has several approximated acceleration algorithms. However, no sophisticated method of acceleration exists for parameter adaptive filters or any other complex filter. For this case, simple subsampling with code optimization is a unique solution. Under the current Moore’s law, increases in central processing unit frequency have stopped. Moreover, the usage of more and more transistors is becoming insuperably complex due to power and thermal constraints. Most central processing units have multi-core architectures, complicated cache memories, and short vector processing units. This change has complicated vectorized programming. Therefore, we first organize vectorization patterns of vectorized programming to highlight the computing performance of central processing units by revisiting the general finite impulse response filtering. Furthermore, we propose a new vectorization pattern of vectorized programming and term it as loop vectorization. Moreover, these vectorization patterns mesh well with the acceleration method of subsampling of kernels for general finite impulse response filters. Experimental results reveal that the vectorization patterns are appropriate for general finite impulse response filtering. A new vectorization pattern with kernel subsampling is found to be effective for various filters. These include Gaussian range filtering, bilateral filtering, adaptive Gaussian filtering, randomly-kernel-subsampled Gaussian range filtering, randomly-kernel-subsampled bilateral filtering, and randomly-kernel-subsampled adaptive Gaussian filtering.

Knowing the metal content of electronic waste is essential to evaluate metal recovery. Lack of a standard method for digestion of precious metals from electronic waste has resulted in difficulty in comparison to the efficiency of recovery. In this study, different precious metal digestion methods and economic value of precious metals from different types of waste printed circuit boards in different fraction sizes, including computer printed circuit boards, mobile phone printed circuit boards, television printed circuit boards, fax machine printed circuit boards, copy machine printed circuit boards, and central processing unit were examined. The optimal digestion method using aqua regia, hydrogen peroxide, hydrofluoric acid, and boric acid was adopted. The precious metal content was analyzed to answer what precious metals and types of printed circuit boards is preference. The results presented the following order of total value of precious metals ( $$\sum {W_{ti} \Pr_{ti} }$$ ): central processing unit > Mobile phone > Copy > Fax > Computer > Television. Among the precious metals, gold and palladium were, respectively, attributed to the highest value distribution. The average values of the precious (gold and palladium) and all of the metals of electronic waste are about 19 and 21 times higher than the average cost of the world’s top ten mines.

There are two main types of computer namely the digital computer and the analogue computer. The digital computer consists essentially of an input, a processing facility, and an output. The input relates to data, the central processing unit (CPU) and its associated memory etc. to the processing facility and the output to the answer the CPU produces. If the central processing unit is a microprocessor, then the computer is called a microcomputer. Such a computer can handle only one job at a time and when many functions have to be carried out simultaneously a mainframe computer is used.