Chapter 4 The Emerging Landscape of Computer Performance Evaluation

The design of computer games can be a powerful motivator as students learn about computer architecture and design. Students in classes where computer designs are developed and implemented (usually on Field Programmable Gate Arrays (FPGAs)) seem much more highly motivated if their computer design can be used for something visual and interactive when the project is complete. However, ensuring that the student teams can have a working game by the end of a semester requires careful planning of how their computer designs will interact with the world. Keyboard inputs and VGA outputs are a relatively simple set of I/O interfaces that open up significant new potential for development of game applications on the student's own computer designs. In this paper we describe the curriculum of a computer design course that uses game design as a carrot to encourage active student exploration and deeper understanding of computer architecture, I/O subsystems, and computer implementation.

This paper discusses the design of a real-time computer. The computer's design requirements, design decisions, and architecture are summarized. The paper discusses how the design requirements influenced the computer architecture. The system's three upward compatible addressing options (real, base, virtual) are also discussed.

Chapter 1 - Impact of VLSI on Computer Architectures

Design rules are directives that guide the design process towards the product. They are often specific descriptions of decisions and acts, which, taken as a whole, make up a design. Sometimes numeric, sometimes verbal, and most often visual or spatial, these descriptions have formed the core of analyses and recreations of design thinking since early history, with the most recent connotations arising in design computing. This issue of the Network Nexus Journal is dedicated to Lionel March, whose seminal contributions to computational art, architecture and design have profoundly influenced our understanding of creative thinking since the 1970s. As the preparations ensued for the tenth Nexus conference ‘‘Nexus 2014: Relationships between Architecture and Mathematics’’ (Ankara, 2014), it was decided that one of the sessions, Rule-Based Design, was to celebrate the legacy of Lionel March in the year of his 80th birthday. Four of the papers presented in that session in Ankara have found their way to this special issue. When Lionel could not attend the conference personally, Kim Williams and I pursued the idea of a celebration in other forms. I am grateful to Kim, who then invited me to guest edit this issue and gave me the chance to bring together texts by prominent scholars of computational design and architecture with much appreciation for Lionel’s presence in the field. In line with the breadth of the impact that Lionel March has had in the field, the issue offers fourteen texts on a variety of topics and approaches of research. Seven of the papers focus on design ontologies, typologies, generative specifications and generating designs that range in scale from the city to furniture. Nine of the papers, some overlapping with the above seven, either directly focus or refer to shape grammars, a computational theory of shapes and visual thinking in design. Among

Students learn better when they both hear and do. In computer architecture courses “doing” can be difficult in small schools without hardware laboratories hosted by computer engineering, electrical engineering, or similar departments. Software solutions exist. Our success with George Mills' Multimedia Logic (MML) is the focus of this paper. MML provides a graphical computer architecture solution with convenient I/O support and the ability to build and emulate a variety of computer designs. It has proven highly motivational to upper division computer science students designing and constructing emulated computers. Student projects resulted in excellent student understanding of the detailed inner workings of computers. Students also developed better teamwork skills and produced useful training aids for the lower division computer organization class. Designs implemented include 8 bit and 16 bit von Neumann and Harvard architectures, from single cycle to 12 cycle instructions. Issues resolved during the learning process include timing, initialization, instruction set architecture, and I/O and assembler design. We discuss pedagogical issues involved in using MML to implement instructor and student computer designs. MML is compared to using a hardware-based Intel 8085 microprocessor basic systems course.

Computing performance evaluation is one of the important technical means of computer architecture research. Scientific and fair evaluation of computer performance and evaluation of processor performance rely on general benchmark test suites, which play a strong role in promoting the development of general-purpose processors. This paper introduces the development status of classification, characteristics and evaluation of the benchmark assembly, and realizes the comprehensive evaluation of various performances such as integer operation and floating-point operation for domestic processors with different instruction set architecture in China. This paper selects a variety of domestic processors with different architecture and Intel processors to quantify the performance of the experimental results, and master the development level of domestic general-purpose processors, which plays a vital role in the development of my country’s industrial control field. Experiments show that the performance of domestic general-purpose processors for integer computing is much lower than that of Intel processors, and the performance of domestic general-purpose processors for floating-point computing is significantly improved. However, there is still a significant gap between the performance of domestic general-purpose processors and Intel processors.

The overview ofsystemdesignandsoftware architecture ofthedistributed control computer (DCC)of anelectric locomotive ispresented. TheDCC isorganized as alocal computer network withthemaster-slave nodeaccess methodwithadualserial bus.Usertaskactivities innodes areorganized by thepreemptive RealTimeOperating System withdynamic planning orbysimple static executive. Networkcommunication services areuniformly usedinall nodestosupportreliable anduserfriendly transfer of process datainside DCC.Thesystemdesign isbasedon criteria asfunctionality, reliability, faulttolerance and maintainability I.INTRODUCTION A control computer of electric locomotive will demonstrate commondesign issues andmethodology of computer system design andsoftware architecture. An electric locomotive as complex of electric drives, pneumatic brakes, security devices, engine driver stands andmanyother parts canbeseenfromsoftware design point ofviewasa mid-range design problem. The software architecture ofcomputer controlled systems has manymodifications anddepends ontheapplication size, required speed, available design time,budgetsize, experience ofsoftware designer andmanyother factors. In simple drive systems (locomotive isnotthecase) with sufficient numberof hardware interrupt resources interrupt-background orinterrupt-no-background

NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract A Microprogrammable Simulator for Logic Design Dick K. Blandford University of Evansville Abstract A class in logic design is a mainstay of most electrical and computer engineering programs and is typically taught in the sophomore year. Such courses cover Boolean algebra, combinational and sequential logic design, logic circuit analysis, and programmable logic devices. Many also provide an introduction to register level design and computer architecture. This paper presents the details of a simulation program that allows students to write microinstructions and some machine code for a simple machine. The program presents an easy-to-use graphical user interface and has options for a two-level and three-level pipelined machine. The program is currently in use in a sophomore level course in logic design as a mechanism to illustrate how a computer works and to introduce computer architecture concepts. I. Introduction Microprogramming is a concept dating back to the early 1950's1 and is widely used in the design of modern computers. The concept is easy to understand and presents a general solution to the control problem for a central processing unit. Students who understand how microprogramming works from a logical point of view have insight into the inner workings and magic of digital computer systems that is difficult to obtain otherwise. An animated simulation of a microprogrammed computer in which a user can "see" the bits interacting with the hardware provides a vehicle for teaching what microprogramming is all about. The software described in this paper runs under the Windows XP operating system and is used in several projects in a sophomore-level electrical engineering class on logic design. It allows students to microprogram a simulated 8-bit computer and to visualize such architectural features as pipelining, the stored program, and the arithmetic and logic unit (alu) loop. II. Characteristics of the simulated machine The simulated machine is loosely based on the Intel 8080 8-bit cpu that dates back to the mid seventies. This machine has roughly the same register set, accumulator-based architecture, and ALU functions. It is however, microprogrammed (the 8080 was not) and it can be used in a pipelined mode (the 8080 had no pipeline). The architectural features of the machine are as follows: • 16-bit address bus • 8-bit data bus Proceedings of the 2005 American Society for Engineering Education Annual Conference & Exposition Copyright © 2005, American Society for Engineering Education

Performance evaluations often receive insufficient attention during the design of a computer system due to the cost of modelling and the lack of quantitative values for model parameters. Nevertheless, cost could be reduced significantly and values could be better estimated if information which already emerged in component designs was made available. In this contribution a concept is presented which links the different “worlds” of computer design, CPU design, and performance evaluation to enable the exchange of information. Generic objects for the hardware components and for the workload predefine a hierarchy of control flow models with associated tasks. Thus, results from CPU analyses can be used in computer system models to describe the CPU behaviour. Just as results from computer analyses can be used for a CPU design. The workload consists of CPU instructions, base algorithms, and processes. Standard instructions support the specification of a CPU's instruction set, base algorithms represent the workload for CPUs and realize an interface to the computer system models where the workload is composed of base algorithms. The i/o-behaviour of a CPU model for the different base algorithms is recorded and re-executed in a computer system model.

Autonomous robotic wheelchairs are widely discussed in recent years. Most of autonomous robotic wheelchairs were developed based on rich computation architecture to deal with complicated navigation efforts such as personal computers or embedded computers. However, such rich computation architectures increase cost of robotic wheelchair when compared to conventional powered wheelchairs. At the same time, large amounts of energy consumptions, lower reliability, and inefficient size of personal computers reduce the practicability of robotic wheelchair. In this paper, we present a low cost solution to solve complicated wheelchair navigation problem based on distributed computing architecture. This solution is developed based on the programmable System-on-Chip (PSoC) computing and control architecture. The tasks within autonomous navigations are categorized into human machine interface, sensor collection, fuzzy logic based navigation functions, closed loop motion controller, and these tasks are individually implemented using the PSoC. Finally, the task oriented PSoC are integrated and fused to perform autonomous navigations of robotic wheelchairs. Consequently, the proposed PSoC based distributed computing architecture was successfully implemented and experimentally tested. The navigation results were verified using the results inferred from the personal computer based computing architecture.

The process of evaluating the effectiveness, speed, and general capabilities of a computer system that is embedded inside a larger device or system and created for a particular purpose is known as embedded computer performance evaluation. Specialized computing systems called embedded systems are built into a wide range of gadgets, including medical, industrial, , automotive and consumer electronics. In this manuscript, Optimized Meta-path extracted graph neural network for embedded computer performance evaluation model(MEGNN-EC-PEM) is proposed. Initially, the input data is obtained from real-time sensor measurements and system metrics for model training and testing. The input image is pre-processed using Orthogonal Master-slave Adaptive Notch Filter (OMANF) and it removes the noise from the collected data. Then, the pre- processed data are fed to embedded computer performance using Meta-path extracted graph neural network (MEGNN). In general, MEGNN does not express adapting optimization techniques to determine optimal parameters to assure precise embedded computer performance evaluation model. Hence, the Hunter–prey optimization algorithm (HPOA) is used to optimize Meta-path extracted graph neural network which accurately categorized embedded computer performance. Then, the proposed MEGNN-EC-PEM is implemented and the performance metrics like Modelling Accuracy, latency, Throughput, memory cost and Energy Consumption are analyzed. The performance of the MEGNN-EC-PEM approach attains 19.41%, 20.08% and 32.57% higher modelling accuracy, 22.41%, 23.08% and 24.57% lower latency and 23.01%, 23.08% and 24.07% higher throughput when analyzed through existing techniques like a state-based modelling approach for effective performance evaluation of embedded system architectures at transaction level (SMA-EPE-ESAT), Evaluating the performance of pre-trained convolutional neural network for audio classification on embedded schemes for anomaly detection in smart cities (PCNN-ACES-ADSC) and Animal behaviour classification via deep learning on embedded systems (ABC-VDL-ES) methods respectively.

We talk about the quantitative approach to computer architecture in this paper. We also go over Amdahl's Law, scalability, parallelism, and the principle of locality in relation to quantitative measurement. We also demystify computer architecture by focusing on smart technical design and cost- performance-power trade-offs. In the context of computer architecture, we think the field has continued to develop and move toward the exacting quantitative foundation of venerable scientific and technical disciplines. The pipelining principles in processor design are the focus of this study.The fundamentals of the instruction pipeline are covered, and an example-based explanation of how to reduce a pipeline delay is provided.The primary goal is to comprehend how a processor's pipeline functions.The different risks that lead to pipeline deterioration are described, along with ways to reduce them. Architecture-based development environments are emerging as a useful tool for building reliable distributed systems. By means of the abstract characterization of intricate software Software reuse and evolution are encouraged in terms of system topologies that involve the interface- level interaction of software parts. Furthermore, as evidenced by research findings in the field of software architecture, it becomes possible to offer formal annotations for the accurate characterization of configuration behavior together with related CASE tools for automated analysis. Nevertheless, while being essential to attaining software resilience, software fault tolerance—and specifically exception management in that context—has received little attention. Keywords: Instruction Pipeline ,Arithmetic Pipeline, Hazards

ABSTRACTThis article documents and reflects upon a pedagogical project aimed at fostering critical engagements with technology in the context of a graduate research and learning laboratory at the nexus of computer science, design, engineering, and architecture. With the notions of critical technical practice and reflective practice as touchstones, the project links a specific tradition of twentieth century design pedagogy to critical sensibilities drawn from the field of science and technology studies (STS) in a space we call the ‘research studio.’ The methods and examples presented illustrate how this hybrid pedagogical model can cultivate the critical imagination of learners – their ability to place critical and sociohistorical reflection at the centre of creative technology design – and show that the fields of design and STS offer distinct but mutually enriching traditions of learning and research. The article offers insight to educators and researchers across STEM and humanities fields interested in engaging with technologies not merely as subjects but also as vehicles of scholarly and creative inquiry.

The MIPS computer architecture is widely used in undergraduate computer architecture and organization courses because of its straightforward design. MIPS is the primary example of the popular textbook Computer Organization and Design [2], used at over 400 universities. We describe a GUI, Java-based simulator for the MIPS assembly language, with characteristics that emphasize usefulness to undergraduate computer science students and - importantly - their instructors.Java and Sun are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries.

I shall attempt in this paper to record my own personal impressions of the way in which computer architecture and designers' objectives have changed during the period that has elapsed since the first stored program computers were being designed 25 years ago. I shall be concerned with the generally accepted state of the art at any time, rather than with the new ideas that were emerging in the more advanced centers. I shall not attempt to track innovations to their source nor to assign dates to them. For convenience of presentation, but for no other reason, I shall divide the period into three phases of very roughly equal duration. I shall end with some remarks about the way thinking has developed on the subject of memory hierarchies, this being one that can be traced through all three phases.