Characteristics of Organic-Based Thermal Interface Materials Suitable for High Temperature Operation

The development of high power and compact size semiconductor packages lead to the challenge in the need of high thermal dissipation design. For package level thermal solution, metal (especially copper) heat spreader and metal/metal-oxide filler thermal interface material are widely adopted. However, the thermal performance of packages is limited by isotropic conductive behavior of most of these materials. The thermal conducting performance could be further improved by directing the heat transportation in the direction desired, for instances the in-plane dissipation for heat spreader and the out-of-plane dissipation for thermal interface material. This present study reported the successful adoption of anisotropic thermal conductive pyrolytic graphite sheet as heat spreader and vertically aligned graphite sheet as thermal interface material in semiconductor package, individually. The Joint Electron Device Engineering Council standard still air junction to ambient measurement experiment shows that a flip chip ball grid array package incorporated with a pyrolytic graphite sheet as heat spreader improved thermal resistance of the module by 20%. The thermal dissipation behavior of the module was simulated with a well validated computational thermal dynamics model based on the experimental results. The anisotropic thermal conductive vertically aligned graphite sheet was also adopted as thermal interface material to replace the nowadays grease type thermal interface material. A thermal test chip assembled large size high performance flip chip ball grid array package mounted on a Joint Electron Device Engineering Council defined 4 layers thermal test printed circuit board was chosen as the test vehicle for thermal interface material performance test. The junction to case measurement experiment shows that the package with the anisotropic conductive thermal interface material improved the thermal resistance by 40%. Some novel designs were proposed basing on the application of this anisotropic thermal conductive material as validated by thermal simulation study. Package design guideline basing on the implementation of the anisotropic thermal conductive material will be discussed in this paper.

In large size package, high temperature affects the stability, reliability and service life of electronic components. The thermal interface material (TIM) plays an important role of effectively enhancing the heat transfer in Flip Chip Ball Grid Array (FCBGA) package; therefore reliability of TIM is indispensable especially when the package device needs to withstand wide high and low temperature periods. In this paper, we conduct a detailed analysis of TIM's reliability in large-size FCBGA package by simulating the stress and strain of TIM layer with the finite element software ABAQUS. The stress of TIM in the package is complex and can be affected by multiple factors such as device structure, material parameters, etc. It is necessary to check the model structure and material parameters to correctly understand the stress of TIM in FCBGA. The statistics method is adopted for analyzing the influence of various parameters.

On the influence of lid materials for flip-chip ball grid array package applications

In recent years, more and more devices are designed by high-performance flip-chip ball grid array (FCBGA) packages due to the requirement on large number of I/O pads, small pitch, and high operation frequency of ASIC. Many studies were done on FCBGA packages. Some of these works were focused on thinner structures. In the study of this paper, our targets will be focused on the coreless and standard FCBGA cases. By directly replacing the BT-core of the standard substrate with a thinner build-up dielectric layer, the coreless design is a good choice to decrease the cost. This replacement makes some differences between the standard thick BT-core and the new thinner build-up substrates. Our study analyzes the electrical performance caused by these differences. With the simulation approach, the analyses include the power integrity (PI) and signal integrity (SI) issues in frequency and time domains on both coreless and standard substrates. In the final results, we found that the coreless substrates could get a better electrical performance, for examples, the smaller coupling between the signal nets, the lower impedance of the power delivery system. The results from these analyses could give a useful reference for chip designers while they make a decision on package.

This paper presents a finite element modeling methodology to predict failure during four-point monotonic bend test of flip-chip ball grid array (FCBGA) packages mounted on printed circuit boards (PCBs). Monotonic bend tests are conducted to failure at approximately 4 mm/sec according to IPC/JEDEC-9702 and the strain is monitored by mounted strain gauges. Test conditions are specified through displacement boundary conditions. Models are validated with displacement and strain. We propose a failure criterion based on the typical failure location and assume it to be a material property. Three test vehicles, one single die FCBGA package and two chip-on-wafer-on-substrate (CoWoS) FCBGA packages are used for validation; all test vehicles are exposed die with stiffener ring packages. From these test vehicles, failure occurs most by cratering the board side pad. Using the proposed methodology, the failure strain for a 3.175mm thick Megtron6 board is calculated to be 5975 μstrain without via-in- pad plated over (VIPPO) and 8130 with VIPPO. The failure criterion is then used to study the effect of design parameters on monotonic bend performance. A parametric study finds when the PCB is thick, board parameters are the most important, BGA parameters are next most important, and most package level parameters have little impact.

Thermal interface materials (TIMs), consisting of high conductivity filler particles dispersed in a polymer matrix, are used in thermal management of electronics to bridge the gap between the heat generating components and the heat spreader or heat sink. Without TIMs, there is imperfect contact at the interface, resulting in detrimental chip performance and elevated temperatures that can ultimately lead to failure of the chip. In commercial applications, TIMs are dispensed on the chip, heat spreader, or the heat sink using a nozzle via an automated process. The TIM is then squeezed into a thin layer over the substrate by the alternate component (i.e., the device, heat spreader, or the heat sink), often followed by curing (e.g., at elevated temperature) to form a rigid bond. During squeezing, the particle-laden TIM generally exhibits non-Newtonian behavior and, after squeezing, the particle spatial distribution may be non-uniform. The flow behavior depends on dispense pattern (e.g., dots, lines, star patterns), parameters of the squeezing process (e.g., force and squeezing rate), and the TIM composition (e.g., particle shape, size distribution, volume fraction, and matrix composition). The velocity and applied pressure during squeezing significantly impacts the achievable bond line thickness (BLT) and the particle spatial distribution, which can cause the thermal performance of the TIM to deviate from the vendor-specified thermal characteristics. In practice, the maximum allowable squeeze pressure, which impacts the final BLT, is limited by potential mechanical failure of packaged electronics. There are open questions regarding the effect of squeezing on particle rearrangement and its effect on thermal conduction within the particle network. In this work, X-ray micro-computed tomography (XRCT) is used to measure the spatial distribution of particles in the TIM after (a) dispensing and (b) squeezing processes. A mock TIM with a target of 30 vol% copper microspheres (median diameter 114 μm) is created by handmixing the particles with a UV-curable epoxy. Microstructural features such as the average particle volume fraction, coordination number and radial distribution function (RDF) are computed to gain insights into the particle spatial arrangement in the TIM.

In a flip chip BGA package, thermal interface materials (TIMs) are applied for thermal management between the die and the heat spreader or between the heat spreader and the heat sink to conduct the heat generated in the die during component operation. Without a thermal interface, the die will overheat and the components will not function properly. Advanced microelectronics packaging demands high and dynamic standards of its supplier industries in relation to speed, precision and flexibility. For example, the demands on functionality, power density and performance of the components within a die are largely enhanced along with TIM requirements for higher heat resistance. Manufacturers are being asked to apply TIMs on more dies in more complicated geometries and to dispense them during any packaging process. This brings increased challenges for TIM dispensing equipment, such as the ability to handle abrasive and dry TIMs at a high throughput while maintaining precision and repeatability. A high-precision, high-throughput TIM dispensing process has been developed to fill the gap between the traditional slower dispensing of simple patterns and the challenges from emerging package designs. This process is being used in flip chip BGA production lines in package applications from consumer electronics to automotive products. These production lines are in full 24/7 operation with each dispensing system running at 240 units per hour (uph) for audio-video consumer electronics, 360 uph for CPUs/GPUs on smart phones and 750 uph for automobile control panels and computation servers. In this new dispensing system, the valve can be tightly controlled to achieve high dispensing accuracy at fast speeds. The dispense pattern and route can be modified at no cost, in minutes, and during any step in the design or the assembly stage. Shapes that can be dispensed include dots, lines, boxes and circles with fine height and edge definitions of 25micron and 45micron. The process can cover a wide range of pattern dimensions between 0.5mm and 100mm at flow rates of 30–370 mg/sec at a repeatability of 3–15% three sigma. Even TIM that has viscosity as high as 1500kcPs with a heavy load of large and coarse particles such as metals, ceramic and glass beads can be dispensed using this equipment and process. New equipment and processes are under development to further push the limit on higher throughput and precision, increased flexibility and material dispensability.

In LD end-pumped solid-state laser, the crystal rod is held and cooled by the metal heat sink. The force applied to the side surface of the crystal is non-axisymmetric. Under such circumstances, three kinds of thermal contact conductance (TCC) models are established, including not using thermal interface material, using thermal interface material with its thickness equal to the average thickness of the gaps and using thermal interface material with its thickness much greater than the thickness of the gaps. Regarding to the first two models, the influences of the assembly force and the equivalent root-mean-square (RMS) roughness on thermal contact conductance are discussed based on the Truncated-Gaussian model and the plastic-deformation model. The contact heat dissipation model of the crystal rod and the heat sink is established. For the Gaussian heat consumption, the spatial distributions of temperature inside the crystal with and without thermal interface material are obtained by the finite element method. The results show that without thermal interface material, the thermal contact conductance between the crystal rod and the heat sink changes significantly in the circumferential direction, which reaches a maximum on the bottom of the heat sink groove and a minimum on the contact area of the heat sink couple. With the assembly force increasing and the equivalent root-mean-square roughness decreasing, the thermal contact conductance gets larger and more nonuniform, and the temperature of the whole crystal rod reduces. When the indium foil is used as thermal interface material, the thermal contact conductance gets larger and more uniform, the temperature of the whole crystal rod reduces as well and its distribution is axisymmetric.

Effect of P on interfacial reaction and shear strength for FCBGA packaging with indium thermal interface materials under isothermal aging

Analysis of warpage of a flip-chip BGA package under thermal loading: Finite element modelling and experimental validation

Thermal management of device level packaging continues to present many technical challenges. In the typical chip heat sink assembly, the highest resistance to heat flow comes from the thermal interface material (TIM). The thermal conductivities of TIMs remain in the range of 1-4 W/mK due to the properties and structure of small dispersed solids in polymer matrices. As a result of the rising design power and heat flux at the silicon die, new ways to improve the effective in situ thermal conductivity of interface materials are required. This paper will introduce a unique TIM enhanced with ultrahigh density wafer level thin film compliant interconnects named smart three axis compliant (STAC) interconnects. The MEMS technology based STAC interconnect is directly fabricated onto a silicon wafer and embedded into the TIM to provide an enhanced conductive path between the die/package and the heat sink. Numerical and analytical analyses of the thermal conduction in the TIM embedded with STAC interconnects are performed. The objective of the study is to provide comprehensive design strategies for effective implementation of this type of TIM for specific applications. Parametric studies are conducted to examine the thermal conductivity of the microinterconnect enhanced TIM for varying materials, configurations, and geometry of the microinterconnects. For the modeling, a periodic element model of chip-TIM configuration with top heat sink is developed and maximum temperatures are determined in order to evaluate the conductive effect of the microinterconnect. In addition, an investigation of the conductive transport in a more complicated chip stack is considered. A 3-D thermal analysis is conducted for a multi-chip stack package with and without through-silicon-vias. The numerical results show that the microinterconnects significantly improve the thermal performance of the TIM. Finally, further steps toward achieving a chip-level design optimization and fabrication process using microinterconnects structured TIM is proposed.

Thermal interface materials (TIMs) play a critical role in enhancing the efficiency of next-generation packaging technologies within the semiconductor industry.[1] The increasing heat density in the latest transistor node sizes, coupled with the continuous increase in die sizes, presents a significant challenge for TIM1s. Modern TIM1s used in semiconductor packaging must not only offer remarkably low thermal resistances (<5 mm^2·K/W), but also exhibit exceptional mechanical performance to accommodate the significant warpage resulting from coefficient of thermal expansion (CTE) mismatches in the packages. Recently, researchers have proposed the use of liquid metal embedded elastomers (LMEEs) [2] as thermal interface materials [3] to create a TIM based on LMEEs that can meet the demands of the most challenging applications. In this presentation, we offer material-level characterization and thermal test vehicle (TTV) testing of LMEEs. Our findings demonstrate that achieving an ultra-thin bondline thickness on the order of 20 µm allows us to attain an exceptionally low thermal resistance of less than 5 mm^2·K/W between the die and integrated heat spreader (IHS). Furthermore, we provide insights into the interplay between adhesion, stretchability, and modulus of the TIM. These are crucial factors for ensuring the TIM has the necessary mechanical properties to maintain the integrity of the interface between the die and the heat sink, thus preventing any degradation in thermal resistance following thermal shock tests. In the end, we present data on the in-situ changes in thermal resistance of LMEEs as a function of strain while cured between two silicon dies, shedding light on the thermomechanical behavior of LMEEs.

A thermal interface material (TIM) is a substance that reduces the thermal resistance between a heat source and heat sink, which facilitates heat conduction towards the outside. In this study, a TiO2 nanosphere (NS)-filler based TIM was fabricated via facile processes such as spin-coating and icing methods. Thermal conductivity of the fabricated TiO2 NS-based TIM was enhanced by increasing the loading contents of the TiO2 NS-filler and successfully cooling down the GPU chipset temperature from 62 °C to 50 °C. Moreover, the TIM with the TiO2 NS-monolayer additionally lowered the GPU temperature by 1–7 °C. The COMSOL simulation results show that the TiO2 NS-monolayer, which was in contact with the heat source, boosts the heat transfer characteristics from the heat source toward the inside of the TIM. The suggested metal oxide monolayer-based TIM is an effective structure that reduces the temperature of the device without an additional filler loading, and it is expected to have a wide range of applications for the thermal management of advanced devices.

In the 5G era, the high performance computing (HPC) products play a pivotal role in supporting big data computing, data center transmission and networking applications. For computing performance enhancement, there are two development trends of product design including chip integration and high thermal dissipation. First, integrating the high bandwidth memory (HBM) into the package is a way to achieve both short and high-speed data transmission. In industry, fan-out platform can provide the benefit for die to die interconnection with fine line and the fine pitch bump design. Second, HPC devices bring high power consumption and require a thermal interface material (TIM) with high thermal conductivity for junction temperature reduction of SoC chip, due to the higher junction temperature will have work fail risk of SoC and even affect the nearby HBM. For high thermal TIM, the thermal conductivity of graphite TIM is directional, XY and Z axis are around 10W/mK and 20W/mK, respectively. The heat dissipation are not only through the vertical direction but also partially through the horizontal direction to the surroundings. The outstanding vertical thermal conductivity can effectively reduce the heat from SoC hot spot and reduce the thermal impact on HBM.Compared with normal FCBGA platform, a way to evaluate graphite TIM in FO structure is provided in this study. The maximum junction temperature impact of SoC and HBM is being explored from thermal simulation between different SoC hot spot design including uniform, center and corner conditions. In addition, the top exposed surface of chip module includes multiple interface with silicon and epoxy molding compound (EMC). We address the graphite TIM attaching performance and TIM coverage. Furthermore, through the innovative structure design to add the adhesive around the chip module, TIM coverage can be improved, especially for large package with worse warpage. All of the silicon die, EMC and underfill are pass without crack from SEM inspection, even if a larger HS (Heat Spreader) clamping force is required for graphite TIM. Finally, we have finished and passed the PLR (Package Level Reliability) with temperature cycle test (TCT) and unbiased highly accelerated stress test (uHAST) conditions.

Polymer‐based thermal interface materials (TIMs) with excellent thermal conductivity and heat dissipation capabilities play a crucial role in addressing the issue of heat accumulation in advanced integrated electronics. However, establishing improved surface interactions and complete networks to enhance efficient phonon transfer remains a significant challenge. To tackle this problem, surface modification and ice‐templating techniques are commonly employed to create the robust interface crosslinks and continuously thermal conductive pathways. Herein, 2‐mercaptobenzimidazole (MB) was used as a reducing and modifying agent to functionalize graphene oxide (rGO‐MB) within the three‐dimensional networks, which was prepared using a combination of hydrothermal and ice‐templating methods. As a result, the reduced graphene oxide/natural rubber (rGO‐MB/NR) TIMs exhibited a remarkable through‐plane thermal conductivity of 0.93 W m−1 K−1 with a filler loading of 3 wt%. The enhanced interface interactions between rGO‐MB and NR, combined with the establishment of a three‐dimensional network, significantly contributed to the improved thermal conductivity and heat dissipation capabilities. Moreover, the obtained TIMs demonstrated favorable mechanical properties (5.06 MPa, 502%) and excellent insulation performance (3 × 1013 Ω cm). These findings provide the valuable insights into potential solutions for mitigating heat accumulation issues in next‐generation electronics.Highlights rGO‐MB with thiol groups was obtained by the hydrothermal method. Interactions between rGO‐MB and NR mainly depended on the chemical bonds. rGO‐MB/NR TIMs owned the improved thermal management performance.