Chiplet Package for Automotive and Edge Processors

The rapid growth of urbanization and energy demand has intensified the need for efficient monitoring and theft detection in power distribution systems. The classical electromechanical and non-mechanical meters are inaccurate and prone to manipulation, which has caused utility providers to lose a lot of revenue. The given research provides an IoT-based smart energy meter monitoring and anti-theft device that incorporates embedded voltage/current sensors, tampering detection units, LoRaWAN-based communication, edge analytics, cloud integration, and hybrid detection algorithms. This suggested system uses Raspberry Pi as an edge processor, Azure IoT Hub as a cloud-processing unit, and distributed databases in order to scale data storage. The hybrid CNN-SVM approach is used to identify the abnormal consumption patterns and it is supplemented with the rule-based logic to detect the tampering events that includes reverse current flow and bypass connections. Experimental analysis illustrates that the suggested solution attains an average monitoring accuracy of 98.3% to energy consumption and a theft detection accuracy of 96.8% compared to the baseline models such as SVM, Random Forest and CNN-only models. Security analysis indicates that AES and ECC-based encryption have less than 3.5% overhead which guarantees confidentiality as well as efficiency. The findings confirm the effectiveness, scalability, and feasibility of the suggested system to be used in reality. In the future, this framework will be expanded by introducing federated learning to detect theft privately and verify the use of blockchains to validate energy transactions, which will enhance trust and transparency in smart grids. This is a major contribution that is aimed at developing sustainable, smart, and inaccessible energy distribution ecosystem.

CMOS Image sensors play a vital role in the exponentially growing field of Artificial Intelligence (AI). Applications like image classification, object detection and tracking are just some of the many problems now solved with the help of AI, and specifically deep learning. In this work, we target image classification to discern between six categories of fruits — fresh/ rotten apples, fresh/ rotten oranges, fresh/ rotten bananas. Using images captured from high speed CMOS sensors along with lightweight CNN architectures, we show the results on various edge platforms. Specifically, we show results using ON Semiconductor’s global-shutter based, 12MP, 90 frame per second image sensor (XGS-12), and ON Semiconductor’s 13 MP AR1335 image sensor feeding into MobileNetV2, implemented on NVIDIA Jetson platforms. In addition to using the data captured with these sensors, we utilize an open-source fruits dataset to increase the number of training images. For image classification, we train our model on approximately 30,000 RGB images from the six categories of fruits. The model achieves an accuracy of 97% on edge platforms using ON Semiconductor’s 13 MP camera with AR1335 sensor. In addition to the image classification model, work is currently in progress to improve the accuracy of object detection using SSD and SSDLite with MobileNetV2 as the feature extractor. In this paper, we show preliminary results on the object detection model for the same six categories of fruits.

Giammatteo, Paolo Valente, Giacomo D’Ortenzio, AlessandroIn this paper we present an application targeting an informative totem, with a discussion about its possible usage and the requirements it needs to satisfy. In this regard, we propose a Machine Learning algorithm, a Convolutional Neural Network, performing computation on images taken from a camera on an edge-computing platform. Performance tests on two different edge processors are reported, respectively for a CPU and a GPU, and a comparison with the principal competitors is provided. Our final goal is to lay the foundation for the application of an informative totem in an edge computing regime, which is able to recognize the age and the gender of the person approaching it in order to give a better presentation of its contents.

In the computational offloading problem of edge cloud computing (ECC), almost all researches develop the offloading strategy by optimizing the user cost, but most of them only consider the delay and energy consumption, and seldom consider the task waiting delay. This is very unfavorable for tasks with high sensitive latency requirements in the current era of intelligence. In this paper, by using D2D (Device-to-Device) technology, we propose a D2D-assisted collaboration computational offloading strategy (D-CCO) based on user cost optimization to obtain the offloading decision and the number of tasks that can be offloaded. Specifically, we first build a task queue system with multiple local devices, peer devices and edge processors, and compare the execution performance of computing tasks on different devices, taking into account user costs such as task delay, power consumption, and wait delay. Then, the stochastic optimization algorithm and the back-pressure algorithm are used to develop the offloading strategy, which ensures the stability of the system and reduces the computing cost to the greatest extent, so as to obtain the optimal offloading decision. In addition, the stability of the proposed algorithm is analyzed theoretically, that is, the upper bounds of all queues in the system are derived. The simulation results show the stability of the proposed algorithm, and demonstrate that the D-CCO algorithm is superior to other alternatives. Compared with other algorithms, this algorithm can effectively reduce the user cost.

Agricultural machines (AMs) refer to equipment usually used in agriculture such as tractors, hand tools, and power tools. It reduces the labor work, increases farms produce, enhances goods quality, and reduces farming time and cost-saving. However, the faults in the fuel system, blades, engine of the AM will often result in degraded vehicle performance, compromising the vehicle’s efficiency and strength. To overcome these problems, fault detection algorithms are developed to identify the faults even before they occur with high classification accuracy. The deep convolutional neural network (DCNN) is a popular deep learning model that offers a high classification recognition rate, and it is widely adopted in similar fields for monitoring the health status of machines. Very few state-of-the-art works are available to identify the health state of agricultural machines using deep learning techniques and extracting the acoustic features from an audio recording. The acoustic signal-based agricultural machine health monitoring and fault prediction model using smartphones is a cost-effective option that is deployed in this proposed work. To optimize the network structure of the DCNN, this paper proposes a Levy flight optimization algorithm (LFOA). The DCNN-LFOA model is implemented on the smartphone’s on-board device (OBD) along with the health monitoring application. The LFOA algorithm minimizes the number of neurons in the DCNN hidden layer and the number of input features from the audio recordings and enhances the classification accuracy. The LFOA algorithm provides the optimal solution which is essential in developing a lightweight DCNN model to implement in the edge processor (smartphone). The experimental results prove that the proposed model gives improved accuracy for the six faults to be classified and serves as a new research model to identify the health condition of the vehicles.

We provide a complete performance comparison of two realizations of the convolution, based on the lowering approach and a blocked variant of the direct convolution algorithm. The theoretical analysis focuses on the conventional, high performance implementation of the general matrix multiplication (gemm), which is the key computational kernel underneath these two algorithms. The study leverages a simulator calibrated for the GAP8 edge processor and exploits the determinism of the memory system in this type of architectures to deliver accurate predictions of the arithmetic and data transfer costs.

A single chip rendering engine that consists of a DRAM frame buffer, an SRAM serial access memory, pixel/edge processor array and 32b RISC core is proposed for the low power 3D-graphics in portable system. The 56 mm/sup 2/ prototype integrating edge processor, 8 pixel processors, 8 frame buffers and RISC core is fabricated using 0.35 /spl mu/m CMOS Embedded Memory Logic (EML) technology.

Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and-accumulate (MAC) operations of artificial intelligence (AI) chips. This work presents an static random access memory (SRAM) CIM unit-macro using: 1) compact-rule compatible twin-8T (T8T) cells for weighted CIM MAC operations to reduce area overhead and vulnerability to process variation; 2) an even–odd dual-channel (EODC) input mapping scheme to extend input bandwidth; 3) a two’s complement weight mapping (C2WM) scheme to enable MAC operations using positive and negative weights within a cell array in order to reduce area overhead and computational latency; and 4) a configurable global–local reference voltage generation (CGLRVG) scheme for kernels of various sizes and bit precision. A 64 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 60 b T8T unit-macro with 1-, 2-, 4-b inputs, 1-, 2-, 5-b weights, and up to 7-b MAC-value (MACV) outputs was fabricated as a test chip using a foundry 55-nm process. The proposed SRAM-CIM unit-macro achieved access times of 5 ns and energy efficiency of 37.5–45.36 TOPS/W under 5-b MACV output.

Heavy data load and wide cover range have always been crucial problems for big data processing in Internet of Things (IoT). Recently, mobile-edge computing (MEC) and unmanned aerial vehicle base stations (UAV-BSs) have emerged as promising techniques in IoT. In this article, we propose a three-layer online data processing network based on the MEC technique. On the bottom layer, raw data are generated by distributed sensors with local information. Upon them, UAV-BSs are deployed as moving MEC servers, which collect data and conduct initial steps of data processing. On top of them, a center cloud receives processed results and conducts further evaluation. For online processing requirements, the edge nodes should stabilize delay to ensure data freshness. Furthermore, limited onboard energy poses constraints to edge processing capability. In this article, we propose an online edge processing scheduling algorithm based on Lyapunov optimization. In cases of low data rate, it tends to reduce edge processor frequency for saving energy. In the presence of a high data rate, it will smartly allocate bandwidth for edge data offloading. Meanwhile, hovering UAV-BSs bring a large and flexible service coverage, which results in a path planning issue. In this article, we also consider this problem and apply deep reinforcement learning to develop an online path planning algorithm. Taking observations of around environment as an input, a CNN network is trained to predict action rewards. By simulations, we validate its effectiveness in enhancing service coverage. The result will contribute to big data processing in future IoT.

Despite advancements in automotive safety, motorized two-wheeler accidents remain a leading cause of global traffic fatalities, primarily due to Traumatic Brain Injury (TBI) and delayed emergency medical response. Traditional motorcycle helmets are fundamentally passive devices that dissipate kinetic energy during an impact but offer no preventative measures against human negligence, nor can they autonomously summon aid post-collision. To address this critical vulnerability, this book presents a comprehensive, multi-disciplinary engineering framework for the design, prototyping, and mass-scale implementation of an active, cyber-physical safety ecosystem: the solar-powered, voice-controlled smart helmet. The proposed architecture severs reliance on external power grids by employing micro-energy harvesting via flexible Copper Indium Gallium Selenide (CIGS) thin-film photovoltaics coupled with Maximum Power Point Tracking (MPPT) algorithms. Safety compliance is strictly enforced through a decentralized Vehicle Interlocking System that utilizes 2.4 GHz cryptographic handshakes and a biometric sensor network to mathematically guarantee helmet presence and rider sobriety before enabling the motorcycle's ignition. In the event of an unavoidable collision, the system deploys a zero-false-positive fall algorithm that fuses 6-axis Inertial Measurement Unit (IMU) data through quaternion mathematics, allowing the preemptive FreeRTOS-based edge processor to accurately distinguish between standard riding kinematics and catastrophic impacts. Upon verification of a crash, the helmet immediately transitions into an autonomous global beacon, serializing GPS coordinates via Protocol Buffers and transmitting an SOS payload to emergency dispatchers utilizing MQTT over cellular (LTE-M) and localized V2X (LoRa) networks. By meticulously bridging material science, microelectronics, advanced digital signal processing, and cloud-based IoT infrastructure, this text provides a complete blueprint for the next evolution of vehicular safety, offering a scalable, perpetually powered technological solution to a global public health crisis. Keywords: IoT Emergency Telemetry; Micro-Energy Harvesting; Vehicle Interlocking Systems; Cyber-Physical Safety Systems

With the rise of decentralized computing, such as in the Internet of Things, autonomous driving and personalized healthcare, it is increasingly important to process time-dependent signals ‘at the edge’ efficiently: right at the place where the temporal data are collected, avoiding time-consuming, insecure and costly communication with a centralized computing facility (or ‘cloud’). However, modern-day processors often cannot meet the restrained power and time budgets of edge systems because of intrinsic limitations imposed by their architecture (von Neumann bottleneck) or domain conversions (analogue to digital and time to frequency). Here we propose an edge temporal-signal processor based on two in-materia computing systems for both feature extraction and classification, reaching near-software accuracy for the TI-46-Word1 and Google Speech Commands2 datasets. First, a nonlinear, room-temperature reconfigurable-nonlinear-processing-unit3,4 layer realizes analogue, time-domain feature extraction from the raw audio signals, similar to the human cochlea. Second, an analogue in-memory computing chip5, consisting of memristive crossbar arrays, implements a compact neural network trained on the extracted features for classification. With submillisecond latency, reconfigurable-nonlinear-processing-unit-based feature extraction consuming roughly 300 nJ per inference, and the analogue in-memory computing-based classifier using around 78 µJ (with potential for roughly 10 µJ)6, our findings offer a promising avenue for advancing the compactness, efficiency and performance of heterogeneous smart edge processors through in materia computing hardware.

The deployment of transformer-based language models on resource-constrained edge devices presents fundamental challenges in computational efficiency and memory utilization. We introduce SQ-LoRA (Stable-rank Quantized Low-Rank Adaptation), a theoretically grounded compression framework that achieves unprecedented efficiency through the synergistic integration of adaptive low-rank decomposition, hardware-accelerated structured sparsity, and intelligent hybrid quantization. Our primary contribution establishes the first rigorous mathematical connection between the matrix stable rank and optimal LoRA rank selection, formalized in Theorem I, which provides bounded approximation guarantees. SQ-LoRA implements: (1) adaptive rank allocation via stable-rank analysis to automatically determine layer-wise compression ratios; (2) 4:8 structured sparsity patterns, enabling 2× hardware acceleration on modern edge processors; and (3) a three-tier quantization scheme that combines 4-bit NormalFloat storage with selective 3-bit/8-bit precision to preserve outliers. A comprehensive evaluation on four diverse natural language processing (NLP) benchmarks demonstrates that SQ-LoRA achieves a 320 MB memory footprint (96.7% reduction) and a 10 ms inference latency (91.7% improvement), and maintains 82.0% average accuracy (within 0.15% of the full model). Statistical significance testing (p &lt; 0.001) confirms its superiority over state-of-the-art methods. This framework enables the deployment of sophisticated language models on devices with 2 GB of RAM, advancing practical edge-AI applications.