CIM Framework for Electronics Manufacturing Systems

Abstract:This paper describes the results of a recent field study of computer integrated manufacturing (CIM) adoption strategies in U.S. manufacturing firms. The purpose of the study was to identify the extent to which CIM technologies are in use in U.S. firms, the impact of a facility’s process characteristics on the CIM development process, and the adoption policy being followed implicitly or explicitly. The survey focused on manufacturing process characteristics, the CIM development process, the CIM architecture, and perceived value and benefits. Our results indicate that CIM implementations follow a definite temporal pattern with respect to the adoption of certain information technologies. We also find evidence of labor substitution through CIM, although the direct labor jobs that are lost are partially replaced by engineering and design tasks. While most CIM users find that their CIM projects successfully meet their initial operational goals, the technology seems to be poorly integrated in most sites...

On the formal specification and verification of CIM architectures using LOTOS

Journal of Electronics ManufacturingVol. 03, No. 01, pp. 13-23 (1993) PAPERSNo AccessDesign and development of a generic ECAD interfaceMUI KIANG ANG and ROBERT K. L. GAYMUI KIANG ANGGINTIC Institute of CIM, Nanyang Technological University, Nanyang Avenue, Singapore 2263, Singapore Search for more papers by this author and ROBERT K. L. GAYGINTIC Institute of CIM, Nanyang Technological University, Nanyang Avenue, Singapore 2263, Singapore Search for more papers by this author https://doi.org/10.1142/S0960313193000036Cited by:0 PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail AbstractIn the face of growing competition in the PCB assembly industries, considerable effort has been applied to determine the most effective solutions to the problems of printed circuit board (PCB) design, manufacture and test to meet changing market demands as well as to improve productivity and quality. Conceptually, the ideal solution is believed to lie in the creation of a practical computer-integrated manufacturing (CIM) environment. To achieve this, the integration of computer-aided design (CAD) systems with auto-insertion and placement machines in a flexible manufacturing system (FMS) is a vital requirement. This paper describes the design and development of a generic CAD interface applicable to a wide variety of CAD systems and auto-insertion and placement machines.Keywords:Generic ECAD interfacePCB assemblyPCB assembly FMS FiguresReferencesRelatedDetails Recommended Vol. 03, No. 01 Metrics History Received 1 September 1992 Accepted 1 October 1992 KeywordsGeneric ECAD interfacePCB assemblyPCB assembly FMSPDF download

There are many complex problems in the optimization of an electronics manufacturing environment, and it is the view of the authors that these problems should not be solved and optimized in isolation, but analysed in the framework of a system. A systems approach offers an overall approach for solving problems, and optimizing the whole of the system as well as discrete subsystems. The research introduced in this paper integrates several techniques, namely: Integrated computer aided manufacturing DEFinition (IDEF), and experimental design and response surface methods for the analysis, control and optimization of electronic manufacturing processes. Electronics manufacturing includes three major processes; Printed Circuit Board (PCB) manufacturing, semiconductor device manufacturing and electronics assembly. This paper describes a novel generic systematic methodology that has been used to create a model to optimize the photolithography process in PCB manufacture. For this, photolithography has been considered as a whole system made up of several sub-systems. This is shown in the process map for PCBs that focuses on photolithography and its subprocesses. A model of the manufacturing process is then given with the results of this being validated using an industrial study. Optimized settings for processing equipment are given resulting in an increase in process yield within industry.

The Cambridge Engineering Selector (CES) is a tool that focuses on material, process, and shape combinations of product design. The Resource Consumption Model (RCM) is a tool that focuses on production process resources, resource costs, production volume, production capacity, and manufacturing cycle time. Both tools help identify viable manufacturing process alternatives to meet stated manufacturing objectives.

The research object in the work is the printed circuit boards (PCB) Production technological process using the additive technology of photopolymer 3D printing. The existing problem is that the manufacturing process of single-sided and double-sided PCBs, simple in technology, from the third to the fifth accuracy class, requires the use of a large amount of consumables and technological equipment. In turn, this affects the cost of the product. The research subject is models and methods for manufacturing PCB using photopolymer 3D printing. In order to reduce the cost of materials: film or aerosol photoresist, as well as reduce the number of technological operations, applying photoresist and for the manufacture of PCBs stencils, it is proposed to use photopolymer 3D printing technologies for the manufacture of PCBs. The paper analyzes the costs of Plexiwire Resin Basic Orange Transparen photopolymer resin for the manufacture of single-sided PCBs and calculates the cost of the consumable (resin) compared to the costs of dry film photoresist. 60 % cost of consumables (photopolymer resin) compared to dry film photoresist for making single-sided PCBs. The work is aimed at determining the dependence of the geometric dimensions of the PСВs topology and the consumption of photopolymer resin on the technological parameters of photopolymer exposure. A regression correlation model of the dependence of resin consumption on exposure parameters has been developed and correlation coefficients have been calculated. It has been established that with an increase in the exposure time of the photopolymer resin, the consumption of the photopolymer resin increases and the deviation of the geometric dimensions of the PCBs topology increases, which in turn negatively affects the quality of the product. Therefore, using the obtained regression model, it is possible to calculate the influence of parameters on the PCB topology and reduce the deviation of conductor sizes and resin consumption.

The transition to the production phase of electronic products requires the product design to follow a large set of constraints that ensure that the electronic product will materialize into a viable product. The printed circuit board (PCB) design is a central part of electronic products and therefore is the part where most constraints are enforced. Although PCB designers already address design constraints with the help of Electrical Computer Aided Design (ECAD) tools that can verify product design rules in an automated manner, there are still many product design rules that are left out of the ECAD tools verification engines, in particular the design rules related to PCB manufacturing and assembly. These rules are many times verified by human visual inspection. This fact increases the risk of running into design errors, leading to increased costs during production phase. This paper proposes a rule ontology representing the large range of constraints imposed by the production phase of electronics products. The rule-based ontology is implemented using a Visual Programming Language (VPL) that facilitates the encoding of the knowledge provided by electronics products manufacturing experts. A practical example is also presented, describing a PCB manufacturing rule and its graphical representation.

Printed circuit boards (PCBs) are primarily used to connect electronic components to each other. It is one of the most important stages in the manufacturing of electronic products. A small defect in the PCB can make the final product inoperable. Therefore, careful and meticulous defect detection steps are necessary and indispensable in the PCB manufacturing process. The detection methods can generally be divided into manual inspection and automatic optical inspection (AOI). The main disadvantage of manual detection is that the detection speed is too slow, resulting in a waste of human resources and costs. Thus, in order to speed up the production speed, AOI techniques have been adopted by many PCB manufacturers. Most current AOI mechanisms use traditional optical algorithms. These algorithms can easily lead to misjudgments due to different light and shadow changes caused by slight differences in PCB placement or solder amount so that qualified PCBs are judged as defective products, which is also the main reason for the high misjudgment rate of AOI detection. In order to effectively solve the problem of AOI misjudgment, manual re-judgment is currently the reinspection method adopted by most PCB manufacturers for defective products judged by AOI. Undoubtedly, the need for inspectors is another kind of labor cost. To reduce the labor cost. of manual re-judgement, an accurate and efficient PCB defect reinspection mechanism based on deep learning algorithm is proposed. This mechanism mainly establishes two detection models, which can classify the defects of the product. When both models have basic recognition capabilities, the two models are then combined into a main model to improve the accuracy of defect detection. In the study, the data provided by Lite-On Technology Co., Ltd. were implemented. To achieve the practical application value in the industry, this research not only considers the problem of detection accuracy, but also considers the problem of detection execution speed. Therefore, fewer parameters are used in the construction of the model. The research results show that the accuracy rate of defect detection is about 95%, and the recall rate is 94%. Compared with other detection modules, the execution speed is greatly improved. The detection time of each image is only 0.027 s, which fully meets the purpose of industrial practical application.

Computing environmental life of electronic products based on failure physics

Fluxing underfill materials are widely used in electronics manufacturing to improve reliability performance. The prevailing process of applying fluxing underfill is by dispensing the desired volume onto the printed circuit board with optimized patterns. The underfill cure is accomplished concurrently with solder joint formation in the reflow process. Even though the processing time of applying underfill material by this method is much shorter than that of the conventional capillary flow underfill process, the processing time of underfill dispensing is much longer than other process steps (e.g., printing, chip placement, reflow, etc). The current underfill dispensing process is a bottleneck in the high-speed electronic assembly manufacturing. Besides the long processing time, the underfill dispensing process requires complicated and expensive dispensing machines, which increase the manufacturing cost. In this research, an innovative dispenseless fluxing underfill process and the associated module have been developed to achieve high-speed SMT compatible underfill processing. The underfill application and chip placement are integrated into one process step that is accomplished by one placement machine. The prototyping of flip chip on board assemblies utilizing this innovative process shows dramatically reduced processing time. It also improves the reliability of electronic assembly systems. This invention enables remarkable cost savings from shortening processing time and eliminating the capital cost associated with underfill dispensing machines. The proposed process and module are fully compatible with the current SMT electronic manufacturing infrastructure. The dispenseless underfill process provides a high-speed and cost-effective solution for flip chip, CSP, and BGA electronic packaging assembly.

Minimizing the mean flow time in a two-machine group-scheduling problem with carryover sequence dependency

PurposeTo present a methodology, including the algorithms, to quantify the risk of failure from tin whiskers and to present a dynamic risk trend based on the distribution of each of the whisker growth parameters, generated from experiments over a period of time. This paper also aims to demonstrate the practical application of the methodology developed.Design/methodology/approachThis paper has been written to provide a methodology to assess tin whisker risk due to fixed whiskers in electronic products. The risk assessment process has been detailed in the paper. To demonstrate the usefulness of the methodology, a tin whisker risk assessment was conducted for a printed circuit board (PCB) in operation.FindingsBased on the experimental tin whisker growth data it is observed that growth rates of mean length and average density decrease with time. Based on the risk assessment, it was estimated that for the common matte tin over copper finish, the failure risk for the circuit card assembly was 4 per cent over 20 years. It was recommended that, for this product, components with bright tin lead finish should not be used. It was also found that the effectiveness of the conformal coating on this PCB is limited by the relative risk of the components on the board.Originality/valueThe paper provides a new methodology to assess fixed tin whisker risk in electronic products. The methodology provides a dynamic risk trend with time because the algorithm incorporates distributional data of whisker growth and the distributional data as a function of time. This type of assessment was lacking in the previous studies.

The rapid growth of modern technology place greater demand on electronic products’ performance and quality. As for the printed circuit board (PCB) assembly of electronic components through surface mounting technology (SMT), high-pixel charge coupled device (CCD) can only screen local images during image collection because of its limited vision. A rapid image mosaic technology has been proposed to seamlessly stitch the local images with overlapping boundaries. The complete image of PCB assembly has been acquired through rapid area matching method within double Mark points and Mark circle. The experiment results show that this method can greatly reduce the image-mosaic time and fairly improve the real-time performance of modern automatic optical inspection (AOI) equipment. Furthermore, such method avoids the alignment error from the characteristic points for noise jamming or noise shielding, and therefore obtains better robustness.

The objective of this study is to investigate the environmental impacts of a printed circuit board (PCB) manufacturing plant through streamlined life cycle assessment approach. As a result, the most effective recommendations on minimizing the environmental impacts for the mentioned sector are revealed and first steps towards establishing a country specific database are taken. The whole PCB production consists of two consecutive stages: namely board fabrication followed by the manufacturing of PCB. Manufacturing of PCB contributes the highest shares to freshwater aquatic ecotoxicity potential (FAETP) and ozone layer depletion potential (ODP). Eighty-nine percent of FAETP is found to be generated from the manufacturing of PCB. Almost all of this contribution can be attributed to the disposal of copper containing wastewater treatment sludge from etching operations to incineration. On the other hand, PCB manufacturing has 73% share in total ODP. Within the manufacturing of PCB, as etching operations are found to be of importance for all the impact categories except eutrophication potential (EP), it is recommended to focus further studies on in-plant control of etching.

Electroless nickel (Ni)/immersion gold (Au), an alternative metal finish on printed circuit board (PCB), has been used successfully for many electronic products. However, brittle fracture of PBGA packages soldered on this metal finish was reported recently by several companies. This paper describes brittle fracture in mechanical testing of thermal enhanced, cavity-down PBGA packages, in the as-reflowed and the aged conditions. In the as-reflowed condition, the fracture is a cleavage between PBGA solder balls and PCB conducting pads. The fracture loads, determined from four-point bending, were typically half of that for peeling off PCB conducting pads. Failure analysis showed that the fracture occurred at the interface between Ni/sub 3/Sn/sub 4/ and Ni-P. Three possible failure mechanisms were explored: (1) phosphorous segregation at the interface, (2) contamination or oxidation during the Ni-Au plating or after plating via diffusion, and (3) brittle fracture of Ni-P and Ni/sub 3/Sn/sub 4/. After aging at 150/spl deg/C for a few days, the AuSn/sub 4/ particles, once in the interior of solder joint in the as-reflowed condition, migrated onto the interface. The weak adhesion between Ni/sub 3/Sn/sub 4/ and AuSn/sub 4/ resulted in a more brittle fracture than that before the aging. This Au-related brittle fracture occurred although the Au concentration in solder joint was only 0.1 wt%, much less than 3 wt%, the rule of thumb concentration for brittle solder joint. The Au-related interfacial fracture may be eliminated by reflow after the aging which moved the AuSn/sub 4/ back to the solder joint interior.