Circulating Current Suppressing Control’s Impact on Arm Inductance Selection for Modular Multilevel Converter

The arm inductors utilized in a modular multilevel converter (MMC) can suppress the MMC circulating current, fault current, and output current, and circulating current ripples. This paper presents a four-step design and optimization method for the MMC arm inductor. The first step is the define the requirements and specifications of the arm inductor based on the MMC ratings and detailed modeling, in order to define the core material and select the appropriate winding wire as a second step. The third step is to develop a multi-objective optimization for the core design of the arm inductor, while the considered constraints are area product, maximum magnetic flux density, and window area, which is here done based on a Non-dominated Sorted Genetic Algorithm (NSGA-II). The objective functions are inductor total mass, total volume, total power losses, total core length, and air gap length. Finally, using the average ranking (AR) method, the best optimal solution is selected from the Pareto solution provided by NSGA-II.

The modular multilevel converter (MMC) is one of the most promising topologies for high- and medium-voltage applications. However, the conventional MMC relies on large arm inductance and complicated feedback control to maintain submodule (SM) capacitor voltages balanced, which requires a large number of voltage sensors and complicated arm current control loops. In contrast to the conventional perspective, the MMC can be regarded as a derivative from the general multilevel topology based on switched-capacitor (SC) structure. The SC structure endows excellent properties to the MMC, such as minimum or no arm inductor and automatic SM capacitor voltage balancing capability. This MMC with minimum or no arm inductor is named as SC-MMC. Since the arm inductances are very small, the SM capacitor voltages can be balanced automatically. Small stray/parasitic inductance is enough to limit inrush current during SM's switching instants to the rated current level. To unleash the automatic SM capacitor voltage balancing capability of the SC-MMC, a Y-matrix modulation (YMM) has been proposed, which does not require closed loop control or any sensor, has no limitations on the number of SMs, and works for both half-bridge and full-bridge SMs. An unresolved issue of the emerging YMM is that, in the published literature, the existence of the Y matrix with full rank has not been proved theoretically beyond the observation for the SC-MMC when the number of SMs is large. In this paper, an analytical proof of the existence of the full rank Y matrix is provided, which implies the automatic voltage balance of SMs for the MMC with arbitrary number of SMs in each arm. Simulation results using the YMM on a 21-level SC-MMC with minimum arm inductance are provided to verify the voltage balance theory/observation of the SC-MMC using the YMM.

The transformer-less modular multilevel converter (MMC) DC-DC converter can achieve direct DC-DC conversion without an intermediate AC transformer. In this paper, a transformer-less MMC DC-DC converter topology with bi-directional DC fault blocking capability is proposed. The proposed converter comprises half bridge submodules (HBSMs) and full bridge submodules (FBSMs). Use of FBSM eliminates the large AC filter which is normally required in the transformer-less topologies. Moreover, the proposed topology has the capability to block the DC fault at either DC side. Once an DC fault is detected, the switches in SM are blocked and the capacitors of HBSM in one DC side are inserted in the fault circuit path. The fault current charges the inserted capacitors and thus reduces to zero quickly. The performance of the proposed topology is validated in a study system using a real-time simulation tool.

Although the control of modular multi-level converters (MMCs) in high-voltage direct-current (HVDC) networks has become a mature subject these days, the potential for adverse interactions between different converter controls remains an under-researched challenge attracting the attention from both academia and industry. Even for point-to-point HVDC links (i.e., simple HVDC systems), converter control interactions may result in the shifting of system operating voltages, increased power losses, and unintended power imbalances at converter stations. To bridge this research gap, the risk of multiple cross-over of control characteristics of MMCs is assessed in this paper through mathematical analysis, computational simulation, and experimental validation. Specifically, the following point-to-point HVDC link configurations are examined: (1) one MMC station equipped with a current versus voltage droop control and the other station equipped with a constant power control; and (2) one MMC station equipped with a power versus voltage droop control and the other station equipped with a constant current control. Design guidelines for droop coefficients are provided to prevent adverse control interactions. A 60-kW MMC test-rig is used to experimentally verify the impact of multiple crossing of control characteristics of the DC system configurations, with results verified through software simulation in MATLAB/Simulink using an open access toolbox. Results show that in operating conditions of 650 V and 50 A (DC voltage and DC current), drifts of 7.7% in the DC voltage and of 10% in the DC current occur due to adverse control interactions under the current versus voltage droop and power control scheme. Similarly, drifts of 7.7% both in the DC voltage and power occur under the power versus voltage droop and current control scheme.

DC fault current limiting effect of MMC submodule capacitors

This paper proposes a novel fault ride-through strategy based on modular multilevel converter (MMC) inner capacitor energy storage (FRT -CES) to cope with dc short-circuit fault. The previous studies normally focus on the dc-side dynamic process during riding through the dc fault, but ac-side characteristics are less considered. Once dc fault occurs, a sudden large ac power loss may lead to frequency oscillation and voltage instability for ac grid system, especially in the high voltage large power occasion. With the adoption of FRT -CES, MMC inner stored energy is utilized to improve dynamic regulation of MMC ac-side power. Whatever level dc voltage drops to due to different faults, FRT-CES can regulate MMC ac-side power smoothly on its own and makes MMC transmit active power to ac grid as much as possible. Simulation results under different conditions of dc voltage sag are provided to demonstrate the validity of the proposed FRT-CES in three-phase hybrid MMC.

Modular multilevel converter (MMC) based high voltage direct current (HVDC) systems are quite popular in high power transmission systems as it offers low losses, high quality output voltage, modular and scalable structure as compared to the two level voltage source converter based HVDC systems. However, inability to block dc fault current is a major concern of conventional MMC-HVDC system, especially for the overhead HVDC system. In this paper, the performance of conventional MMC with half bridge submodules is analyzed for dc side fault. In the event of a dc side fault, the conventional MMC acts as an uncontrolled diode rectifier and feeds very high current to dc fault. To tackle this problem, different techniques have been discussed in the literature. This paper gives a brief overview of dc fault tolerant techniques discussed in the literature. Moreover, in this paper, a detailed comparison between different hybrid topologies with dc fault tolerant capability is performed on the basis of required number of switches and capacitors. Furthermore, the fault tolerant capability of MMC with bipolar (full bridge) submodule is experimentally validated.

A multi-terminal high voltage DC (MTDC) grid, is an optimum and cost-effective transmission network to minimize the energy crisis worldwide largely. However, the core demand for a fast DC protection scheme with an extraordinary strict fault clearance time of a few milliseconds, is a key research gap in this network, holding back its development and scalability. To bridge this gap, this paper proposes a novel protection scheme for a meshed MTDC grid. The main goals of the scheme include accurate discrimination of a faulty line, rapid fault detection, fault location estimation, significant fault current reduction, and fully selective isolation of only the faulted line, while continuing normal power flow in the healthy grid zones. Reliability of the scheme for long and extra-long-distance power transmission is increased by aiding the differential protection and Type-D traveling wave (TW)-based algorithms utilizing the distributed optical current sensing technology with the other auxiliary methods and backup plans. These auxiliary methods include independent discrete wavelet transform (DWT), current derivative polarity principles with a minimum sample (short time) window, overcurrent relays, and AC circuit breakers (ACCBs). A faulty segment of a transmission line is accurately discriminated from the healthy ones by measuring a series of multi-point differential currents on it. A faulty line at a particular DC node is accurately discriminated using the differential protection by measuring the current flowing into or out of each line from each side at every node to obtain the algebraic sum. The current sum of a real-time local transient data and a delayed remote data is compared to a preset threshold level. DC fault current is significantly reduced below the breakable levels by coordinating bidirectional hybrid DC circuit breakers (HDCCBs) with the active and passive fault current limiters (FCLs) and the half bridge-VSC-based modular multilevel converters (MMCs). The proposed concepts are successfully verified by the simulation results under a variety of fault scenarios and are found to be accurate.

The digital control system of modular multilevel converters (MMCs) normally synchronizes with the switching actions. The switching frequency of an MMC is generally selected as low as possible from an efficiency point of view, which leads to an unavoidable and relatively long time delay in the control system. Such a time delay might deteriorate the MMC performance and even reduce the stability margin by introducing infinite uncertain eigenvalues into the system state functions. Without a proper time-delay model and quantitative system stability analyses, MMCs might suffer from uncertainties and unstable risks during their operations, especially when the switching frequency is low. This paper derives an MMC model considering the time delay in the digital control system. A Pade-based stability analysis method is then proposed, which consists of three steps: information integration and critical eigenvalue extraction, and trajectory visualization and critical angle (CA) calculation, and quantitative assessment and extreme value determination. By the proposed model and method, the critical eigenvalue can be effectively extracted. With the Hopf bifurcation, the time delay in the digital control system induces a pair critical conjugate eigenvalues into MMC systems, which is detected as an instability cause. The CA and the critical impact are defined to quantitatively assess the stability, while selecting the controller parameters and minimum switching frequency. The proposed method for the MMC stability assessment is experimentally verified.

The differential current in Modular Multilevel Converters (MMCs) is inherently subjected to even order harmonics, which are mainly caused by the voltage mismatch between phase legs and dc bus. This issue may exist in both single-phase and multi-phase MMC systems and can be eased by repetitive control based active harmonic suppression methods, which regulate the circulating current through legitimate adjustment of the voltage applied on the arm inductance. Nevertheless, conventional repetitive controllers have relatively slow dynamic response because of the presence of one fundamental period delay, and all the sampled errors in the past one cycle have to be stored for closed-loop control. This paper presents an improved even-harmonic repetitive control scheme that requires less data memory with faster dynamic response. The steady state performance can also be enhanced if system disturbances e.g. frequency deviation are considered. In order to verify its practicality and effectiveness, PLECS simulation and experimental results are presented to show the excellent dynamic response and disturbance rejection of the proposed even-harmonic elimination scheme.

New analysis of VSC-based modular multilevel DC-DC converter with low interfacing inductor for hybrid LCC/VSC HVDC network interconnections

This paper presents deeply analysis and comparison of different modulation techniques for the modular multilevel converter without using arm inductor. In case of PWM, losses are more and Total Harmonic Distortion (THD) performance is very poor. With the introduction of delta modulation in MMC, the losses will reduce and THD will improve. It can be seen that the THD is 4.9% for delta modulation and 3.82% for adaptive delta modulation without using arm inductance but THD is 13.15% for delta modulation with arm inductance. It means THD has been improved without using arm inductance. It has been observed that the adaptive delta modulation has better THD response as compared to delta modulation due to its several advantages. The THD performance has been calculated and mentioned at different modulation indexes. It has been also observed that the THD performance is better with delta and adaptive delta modulation.

— The modular multilevel converter (MMC) is considered to be emerging multilevel topology for medium to high power applications due to its modularity and highly reliable structure. However, large submodule (SM) capacitor voltage ripple and higher circulating current during variable frequency operation is the major drawback of the MMC. In the literature, higher-order harmonic elimination technique is presented to reduce SM capacitor voltage ripple and circulating current. In this article, effect of lower-order harmonics on circulating current is investigated. The effect of second-order fundamental frequency current harmonic I2f on arm inductor is analyzed. Based on detailed analysis, an optimal design method for selection of arm inductor is proposed. Proposed optimal design is capable of reducing the circulating current under variable frequency range as well as SM capacitor voltage ripple remains under specified limit during entire variable frequency operation. A detailed MATLAB model of MMC fed high power medium voltage drive is developed. Experimental setup is also developed to check the effectiveness of proposed optimal design method. Reduction in circulating current and control of SM capacitor voltage ripple is observed for entire range of frequency.

Modular Multilevel Converters (MMC) are known for their high modularity and good quality output power. The problems of circulating current and capacitor voltage balancing for the MMC have been widely studied in available literature but little work is done towards grid current control with fast dynamic response. Conventional current controllers use PI or PR controllers which are slow and thus degrade transient performance of the MMC. Recently reported Model Predictive Control (MPC) methods for MMC aim to control the grid current but MPC suffers from computational burden and difficulties in adjusting of weights. Space Vector based Hysteresis Current Controllers (SCHCC) have been well established for drive applications. In this work, an SVHCC has been developed for a grid connected MMC system. Simulation studies show fast current control for cases of sudden change of active power reference and current reference. The controller exhibits quick tracking of the current reference in all cases. The proposed method has been discussed for a MMC system with three submodules, but it may be extended to any number of submodules and can be easily implemented in a digital controller with less computational effort.

Although the modular multilevel converters (MMCs) that contain submodules (SMs) with negative voltage capability have various advantages, they usually demand many more semiconductors than the conventional half-bridge SM-based MMC (HB-MMC). This study proposes a unidirectional-current clamp-double submodule (UC-CDSM) by combining two unidirectional-current full-bridge SMs (UC-FBSMs) using a shared switching device. The sharing design enables the UC-CDSM-based MMC (UC-CD-MMC) to have 25% fewer switching devices compared with the UC-FBSM-based MMC. The quantity of switching devices is rather similar to that in a conventional HB-MMC while the UC-CD-MMC still retains the advantages, such as low capacitor usage, dc fault clearing capability, and wide-range dc voltage adjustability. Moreover, a unidirectional-current hybrid MMC composed of UC-CDSMs and UC-FBSMs (UC-HYB-MMC) is presented to further enlarge the adjustable range of dc voltage. Detailed comparisons indicate that the UC-CD- and UC-HYB-MMCs can reduce the valve costs by 32% and 25%, respectively, and volumes by 39% and 34%, respectively, compared with HB-MMCs. Simulation and experimental results verify the steady-state and dc-fault clearance of the proposed topologies, and that the capacitor voltages in the UC-FBSMs and UC-CDSMs are well maintained and balanced in the UC-HYB-MMC.