Classifications and graph-based representations of switching functions using a novel complex spectral technique

This special issue of the VLSI DESIGN: an International Journal of Custom-Chip Design, Simulation and Testing is devoted to spectral techniques, new types of decision trees and diagrams, their applications, efficient ways of their calculation and mutual relations between spectral techniques and classical decision diagrams. Manipulations and calculations with discrete functions are fundamental tasks in many areas of Computer Science and Engineering. Many problems in digital system design, simulation and testing can be expressed as a sequence of operations on discrete functions. The performance of Computer-Aided Design systems used in solving various problems in this area strongly depends on the efficiency of representations of discrete functions. Decision Diagrams (DDs) have proved very convenient data structure for discrete function representations, permitting manipulations and calculations with large functions efficiently in terms of time and space. In many applications, as for example those involving large matrices, conventional algorithms are significantly improved by using DDs. In logic design, such applications relate to basic problems of the design, verification, simulation and testing logical networks. Besides Boolean functions, some other types of discrete representations, such as multi-valued functions, cube sets, EXOR-based spectral and probabilistic formulas have to be dealt with. Hence the numbers of different decision trees and diagrams have been introduced for these various applications and representations. The spectral or polynomial representation of Boolean function is obtained by expressing it in terms of an orthogonal basis. The most popular basis is formed by discrete Walsh functions. Note that the spectral and the polynomial representation of a Boolean function are equivalent. The discrete orthogonal functions are referred to as the basis functions when the spectral or abstract harmonic terminology is used and as monomials when the polynomial terminology is used. Such polynomial representations have extensive applications in coding theory and cryptography as well as design of nonlinear filters. Spectral techniques based on Walsh, Haar, Arithmetic and Reed–Muller transforms have been used in digital logic design for more than 30 years. These techniques have been used for Boolean function classification, disjoint decomposition, identification of symmetries, parallel and serial linear decomposition, spectral translation synthesis (extraction of linear preand post-filters), multiplexer synthesis, threshold logic synthesis, state assignment and testing, and evaluation of logic complexity. The renewed interest in applications of spectral methods in design of VLSI digital circuits is caused by their excellent design for testability properties and in their efficiency in Boolean mapping problems. Furthermore, the practical applicability of these techniques was greatly improved with the development of efficient methods that allow calculating and operating on spectra of Boolean functions directly from reduced representations of such functions in the form of arrays of cubes or decision diagrams. Following from these recent developments, techniques have been presented for efficient spectral translation to decompose a circuit into a cascade of two sub circuits: linear block composed of EXOR gates fed by the primary input of the overall circuit. Such linear decomposition drastically simplifies the synthesis task. The choice of suitable linear transformation is based on a complexity measure assigned to each Boolean function that is heuristically related to the complexity of the final circuit implementation. To avoid the experimental costs of computing the Walsh transform, Binary Decision Diagrams (BDDs) based techniques are used. Recently the idea of linear transformations is applied to decision diagrams. By combining powerful spectral linear techniques with variable reordering techniques, it is possible to synthesize large Boolean functions with standard Computer-Aided Design tools that fail otherwise. The areas addressed by this special issue span spectral transforms, their applications and efficient calculation methods through decision diagrams. New spectral decision diagrams are also emerging that support larger data structures allowing more complex discrete representations to be implemented that was previously impossible.

In decision diagrams (DDs) methods for circuit synthesis, it is possible to directly transfer a DD for a given function f into a network realizing f by the replacement of non‐terminal nodes in the DD with the corresponding circuit modules.The chief bottleneck of mapping a DD into a network is the inherent feature that the depth of the network produced, is equal to the number of variables in f . For this reason, it is proposed a method for small depth circuit synthesis through reachability matrices describing connections among the nodes in the DD for f.In this paper, we first generalized DD methods for circuit design to Fibonacci interconnection topologies through the Fibonacci decision diagrams (FibDDs). Then, we extended the small depth circuit synthesis method to FibDDs. In this way, design methods through DDs are completely transferred from Boolean to Fibonacci topologies.

In design systems for digital VLSI (very large integrated circuits), the BDD is used for VLSI verification, as well as for technologically independent optimization, performed as the first stage in the synthesis of logic circuits in various technological bases. BDD is an acyclic graph defining a Boolean function or a system of Boolean functions. Each vertex of this graph corresponds to the complete or reduced Shannon expansion formula. Having constructed BDD representation for systems of Boolean functions, it is possible to perform additional logical optimization based on the proposed method of searching for algebraic representations of cofactors (subfunctions) of the same BDD level in the form of a disjunction or conjunction of other cofactors of this BDD level. The method allows to reduce the number of literals by replacing the Shannon expansion formulas with simpler formulas that are disjunctions or conjunctions of cofactors, and to reduce the number of literals in specifying a system of Boolean functions. The number of literals in algebraic multilevel representations of systems of fully defined Boolean functions is the main optimization criterion in the synthesis of combinational circuits from library logic gates.

In this paper we give a spectral transform interpretation of AND-EXOR representations of switching functions and related decision diagrams in the vector space over GF(2). The consideration is uniformly extended to the Fourier series-like expressions of functions in the complex vector space and the decision diagrams for integer-valued functions. It is shown that the multi-terminal decision diagrams, MTBDDs, and edge-valued decision diagrams, EVBDDs, for integer-valued functions are derived by using the same sets of basic functions already applied for the decision diagrams attached to some AND-EXOR expressions, but considered over the complex field. The algebraic transform decision diagrams, ATDDs, are considered as the integer counterparts of the functional decision diagrams, FDDs, attached to the algebraic transform in the same way as the FDDs are attached to the Reed-Muller expressions. It is shown that the EVBDDs are the ATDDs in different notation.

Ordered Kronecker functional decision diagrams (OKFDD's) are a data structure for efficient representation and manipulation of Boolean functions. OKFDD's are a generalization of ordered binary decision diagrams (OBDD)s) and ordered functional decision diagrams and thus combine the advantages of both. In this paper, basic properties of OKFDD's and their efficient representation and manipulation are given. Starting with elementary manipulation algorithms, we present methods for the construction of small OKFDD's. Our approach is based on dynamic variable ordering and decomposition-type choice. For changing the decomposition type, we use an efficient reordering-based method. We briefly discuss the implementation of PUMA, an OKFDD package, which was used in all our experiments. These experiments demonstrate the quality of our methods in comparison to sifting and interleaving for OBDD's.

A method for the decomposition of systems of completely defined Boolean functions given a two-block partition of the set of variables and a decision algorithm for the partition of this set are proposed. The system of functions is determined by a binary decision diagram, which simplifies the search for the variable partition and the decomposition based on this partition. Results of experimental studies demonstrating the efficiency of the proposed decomposition in the synthesis of logic circuits are presented.

Bent functions are a class of discrete functions which exhibit the highest degree of nonlinearity. As such bent functions form an essential part of cryptographic systems. Original concept of bent functions defined in GF(2) can be extended to multiple-valued case. Multiple-valued bent functions are defined in therms of properties of their Vilenkin-Chrestenson spectra. Decision diagrams are a method of compact representation of discrete functions. Special types of decision diagrams have been introduced for various types of discrete functions. In this paper we demonstrate how Vilenkin-Chrestenson decision diagrams can be used for efficient representation of multiple-valued bent functions.

Resistive Random Access Memories (RRAMs) have gained high attention for a variety of promising applications especially the design of non-volatile in-memory computing devices. In this paper, we present an approach for the synthesis of RRAM-based logic circuits using the recently proposed Majority-Inverter Graphs (MIGs). We propose a bi-objective algorithm to optimize MIGs with respect to the number of required RRAMs and computational steps in both MAJ-based and IMP-based realizations. Since the number of computational steps is recognized as the main drawback of the RRAM-based logic, we also present an effective algorithm to reduce the number of required steps. Experimental results show that the proposed algorithms achieve higher efficiency compared to the general purpose MIG optimization algorithms, either in finding a good trade-off between both cost metrics or reducing the number of steps. In comparison with the RRAM-based circuits implemented by the state-of-the-art approaches using other well-known data structures the number of required computational steps obtained by our proposed MIG-oriented synthesis approach for large benchmark circuits is reduced up to factor of 26. This strong gain comes from the use of MIGs that provide an efficient and intrinsic representation for RRAM-based computing - particularly in MAJ-based realizations - and the use of techniques proposed for optimization.

Loading classical data into quantum registers is one of the most important primitives of quantum computing. While the complexity of preparing a generic quantum state is exponential in the number of qubits, in many practical tasks the state to prepare has a certain structure that allows for faster preparation. In this paper, we consider quantum states that can be efficiently represented by (reduced) decision diagrams, a versatile data structure for the representation and analysis of Boolean functions. We design an algorithm that utilizes the structure of decision diagrams to prepare their associated quantum states. Our algorithm has a circuit complexity that is linear in the number of paths in the decision diagram. Numerical experiments show that our algorithm reduces the circuit complexity by up to 31.85% compared to the state-of-the-art algorithm, when preparing generic $n$-qubit states with ${n}^{3}$ nonzero amplitudes. Additionally, for states with sparse decision diagrams, including the initial state of the quantum Byzantine agreement protocol, our algorithm reduces the number of controlled-nots by 86.61--99.9%.

The problem of implementing Boolean functions in polynomial forms finds applications in the synthesis of logic circuits, in discrete models of system biology. One of the classes of polynomial forms is the class pseudopolynomial forms (PSPF) - expressions that are the sum over modulo two of conjunctions of Zhegalkin polynomials of linear functions. Latest years, the properties of the implementation of Boolean functions in the class have been actively studied PSPF. One of the complexity characteristics of implementing functions in a class psf is the length - the minimum number of terms among all SSPFs that implement the function. The report will present the results of evaluation of the lengths of the system of adder functions and comparator functions in the class PSPF.

In this paper a method of creating layers of feed-forward neural network that does not need to be learned is presented. Described approach is based on algorithms used in synthesis of logic circuits. Experimental results presented in the paper prove that this method may significantly decrease the time of learning process, increase generalization ability and decrease a probability of sticking in a local minimum. Further work and goals to achieve are also discussed.Keywordsfeed-forward neural networklogical circuitparallel decompositionargument reductionpattern recognitionlearning algorithm

The purpose of this work is to investigate some of the algorithms used for representing switching functions by space efficient decision diagrams. This representation is an optimization problem. Adopting the terminology from combinatorial optimization problems, we have:Problem Instance: A multivalued function f(x) where x is a vector, and a storing cost, s(xi), associated with each variable xi in x.Feasible Solution: A decision diagram D (acyclic, directed graph with indegrees of the internal nodes possibly exeeding one) representing f(x).Objective Function: The total storage cost,S(D) = Σ s(xi) for each feasible solution D.xie DOptimal Solution: A decision diagram D representing the function with minimum total storage cost S(D), i.e. a feasible solution which minimizes the objective function.To date, only two algorithms for the construction of optimal decision diagrams with respect to the total storage cost have been developed; Reinwald & Soland's branch & bound algorithm and Thayse's, based on the extension of Shannon's expansion formula. The second algorithm is analyzed and proven to be highly exponential in the number of variables. This comes as no surprise since, in most cases, the construction of optimal decision trees is an NP-hard problem. The construction of decision diagrams is generally more complicated than that of trees. One cannot seriously doubt that the constructions of optimal diagrams is also NP-hard for most costs including the total storage cost. Therefore, a heuristic approach to this problem is needed. Two heuristics, based on the greedy algorithmic technique, are presented. These heuristics with the analysis of Thayse's algorithm constitute the major achievements of this work.

This paper is devoted to the synthesis of combinational logic circuits through computational intelligence or, more precisely, using evolutionary computation techniques. Are studied two evolutionary algorithms, the Genetic and the Memetic Algorithm (GAs, MAs) and one swarm intelligence algorithm, the Particle Swarm Optimization (PSO). GAs are optimization and search techniques based on the principles of genetics and natural selection. MAs are evolutionary algorithms that include a stage of individual optimization as part of its search strategy, being the individual optimization in the form of a local search. The PSO is a population-based search algorithm that starts with a population of random solutions called particles. This paper presents the results for digital circuits design using the three above algorithms. The results show the statistical characteristics of this algorithms with respect to the number of generations required to achieve the solutions. The article analyzes also a new fitness function that includes an error discontinuity measure, which demonstrated to improve significantly the performance of the algorithm.

Reversible circuits are an emerging technology where all computations are performed in an invertible manner. Motivated by their promising applications, e.g. in the domain of quantum computation or in the low-power design, the synthesis of such circuits has been intensely studied. However, how to automatically realize reversible circuits with the minimal number of lines for large functions is an open research problem. In this paper, we propose a new synthesis approach which relies on concepts that are complementary to existing ones. While "conventional" function representations have been applied for synthesis so far (such as truth tables, ESOPs, BDDs), we exploit Quantum Multiple-valued Decision Diagrams (QMDDs) for this purpose. An algorithm is presented that performs transformations on this data-structure eventually leading to the desired circuit. Experimental results show the novelty of the proposed approach through enabling automatic synthesis of large reversible functions with the minimal number of circuit lines. Furthermore, the quantum cost of the resulting circuits is reduced by 50% on average compared to an existing state-of-the-art synthesis method.

Logic functions are usually represented by logical expressions or decision diagrams using AND and OR operators. However, some functions have more compact representations with EXOR operators. This chapter surveys representations of logic functions using EXOR operators.