Clock tree tuning using shortest paths polygon

Unused spare cells occur inevitably in traditional engineering change order (ECO) design flow. It results in inefficient area usage, more leakage, and more IR drop impacts. To tackle these problems, a reconfigurable cell is proposed, which serves the dual purposes of decoupling capacitance and spare cell in this paper. Before ECO is applied, these cells are preplaced as decoupling capacitors. When ECO is applied, these cells are configured as functional cells. To demonstrate the efficiency of our configurable cell, we propose an algorithm for timing closure and IR drop minimization. Compared with traditional ECO flow, our method shows 15% reduction in maximum IR drop and 9% reduction in leakage before applying ECO, and 7% reduction in maximum IR drop after applying ECO, with 10% area of spare cells. In addition, we show that there remain less unsolved timing-violation paths after applying our ECO timing optimization flow due to less IR drop and free selection of ECO gate type.

This paper describes an implementation of a Knowledge Discovery in Databases (KDD) process for extracting the causes of iterations in Engineering Change Orders (ECOs). A data set of approximately 53,000 historical Engineering Change Orders (ECOs) was used for this purpose. Initially, the impact of iterations in ECO lead time and uncertainty is assessed. Subsequently, a semi-automatic text-mining process is employed to classify the causes of iterations. As a result, cost and technical categories of causes were identified as the main reasons for the occurrence of iterations. The study concludes that applying KDD in historic ECO data can help in identifying the causes of iterations of ECO which subsequently can provide a framework for companies to reduce these iterations. In addition, the case represents an example of benefits that can be achieved with the application of KDD in engineering change management.

As design size gets larger and becomes more complicated with feature integration, the runtime for Static Timing Analysis (STA) becomes more of a concern. Due to time-to-market pressure, the validation of the design is performed in parallel with the physical synthesis flow; therefore it is not uncommon to find last minute critical logic bugs during final design integration iterations. However, timing verification needs to be run on full-chip level to ensure that the check is comprehensive. This paper proposes a method to isolate only those logics which are affected by the Engineering Change Order (ECO) for STA. This simplification will allow faster ECO iteration to enable a more efficient timing convergence. The proposed method is also suitable to be used for multithreading in STA engines to speed-up timing verification due to ECO changes. Engineering Change Order (ECO), Static Timing Analysis (STA), Incremental Static Timing Analysis, VLSI design

Due to increasing integrated circuit design complexity, engineering change orders (ECOs) have become a necessary technique to resolve late-found functional errors and/or performance deficiencies. To fix timing violations, gate sizing and buffer insertion are commonly used in postmask ECO. These techniques, however, may not be powerful enough, especially when spare cells are inserted to balance between functional and timing repair capabilities. We propose a postmask ECO technique, called TRECO, to remedy timing violations based on technology remapping, which also supports functional ECO. Unlike conventional technology mapping, TRECO performs technology mapping with respect to a limited set of spare cells and confronts dynamic changes of wiring cost incurred by selection of different spare cells. With a precomputed lookup table of representative circuit templates, TRECO iteratively performs technology remapping to restructure timing critical subcircuits until no timing violation can be further removed. Experimental results on five industrial designs show the effectiveness of TRECO in ECO timing optimization and in timing-aware functional ECO.

Clock trees can be constructed based on static arrival time constraints or dynamic implied skew constraints. Dynamic implied skew constraints allow the full timing margins to be utilized. However, the dynamic skew constraints require a high run-time complexity to be evaluated. In contrast, static arrival time constraints are more restrictive but can be evaluated in constant time. Consequently, there is a tradeoff between timing margin utilization and run-time. In this paper, a scalable clock tree synthesis (CTS) framework is proposed for the construction of low-cost useful skew trees (USTs) with high timing quality. The scalability is based on combining the use of arrival time constraints with virtual minimum and maximum delay offsets, which facilitates that a pair of smaller subtrees can be joined into a larger subtree in constant time. The ability to quickly join subtrees is leveraged to perform a high degree of solution space exploration, which translates into the construction of USTs with low-cost. In particular, clock trees with various routing tree topologies, buffer tree topologies, buffer sizes, and stem wire lengths are explored. Moreover, the arrival time constraints are specified with the objective of being the least restrictive to reduce cost. Furthermore, the constraints are respecified throughout the tree construction process using a slack graph (SG) to expose additional timing margins. The high timing quality is obtained by seamlessly integrating arbitrary timing models using the SG. Finally, the proposed CTS framework is integrated with a clock tree optimization framework to demonstrate that the constructed USTs are capable of meeting timing constraints under the influence of on-chip variations.

3D gated clock tree synthesis (CTS) mainly consists of three steps: 1) abstract clock topology generation; 2) layer embedding for minimal TSV allocation and 3) clock tree routing with gate and buffer insertion. In this paper, a self-tuning spectral clustering based nearest-neighbor selection (SSC-NNS) algorithm with parallel structure is proposed to achieve high time efficiency in clock tree topology generation, with reduced runtime. In addition, a postorder traversal based layer embedding (PTLE) strategy is adopted for determining the embedding layer of internal nodes with minimal TSV usages. Experimental results show that the proposed method achieves 32% and 82% runtime reduction on ISPD2009 and IBM benchmarks respectively compared with the state-of-the-art 3D work. Besides, the TSV count is also reduced by 46% on ISPD2009 benchmarks.

Design companies often outsource their integrated circuit (IC) fabrication to third parties where ICs are susceptible to malicious acts such as the insertion of a side-channel hardware trojan horse (SCT). In this paper, we present a framework for designing and inserting an SCT based on an engineering change order (ECO) flow, which makes it the first to disclose how effortlessly a trojan can be inserted into an IC. The trojan is designed with the goal of leaking multiple bits per power signature reading. Our findings and results show that a rogue element within a foundry has, today, all means necessary for performing a foundry-side attack via ECO.

Modern high-performance System-on-Chip (SoC) design flows highly depend on signoff tools to perform timing-constrained power optimization through Engineering Change Orders (ECOs), which involve gate-sizing and Vth-assignment of standard cells. However, ECOs are highly time-consuming, and the power improvement is unknown in advance. Ever since the industrial benchmarks released by the ISPD-2012 gate-sizing contest, active research has been conducted extensively. Nonetheless, previous works were mostly based on heuristics or analytical methods whose timing models were over-simplified and lacked formal validations from commercial signoff tools. In this paper, we propose ECO-GNN, a transferable graph-learning-based framework, which harnesses graph neural networks (GNNs) to perform commercial-quality signoff power optimization through discrete Vth-assignment. Our framework generates tool-accurate optimization results instantly on unseen netlists that are not utilized in the training process. Furthermore, we implement a GNN-based explanation method to interpret the optimization results achieved by our framework. Experimental results on 14 industrial designs, including a RISC-V-based multi-core system and the renowned ISPD-2012 benchmarks, demonstrate that our framework achieves up to 14X runtime improvement with similar signoff power optimization quality compared with Synopsys PrimeTime.

Single Event Transients (SETs) in clock-distribution networks are a major source of soft errors in synchronous systems. We present a practical framework that assesses SET risk early in the design cycle, before layout and parasitics, using a Vulnerability Function (VF) derived from Verilog fault injection. This framework guides targeted Engineering Change Orders (ECOs), such as clock-net remapping, re-routing, and the selective insertion of SET filters, within a reproducible open-source flow (Yosys, OpenROAD, OpenSTA). A new analytical Soft Error Rate (SER) model for clock trees is also proposed, which decomposes contributions from the root, intermediate levels, and leaves, and is calibrated by SPICE-measured propagation probabilities, area, and particle flux. When coupled with throughput, this model yields a frequency-aware system-level Bit Error Rate (BERsys). The methodology was validated on a First-In First-Out (FIFO) memory, demonstrating a significant vulnerability reduction of approximately 3.35× in READ mode and 2.67× in WRITE mode. Frequency sweeps show monotonic decreases in both clock-tree vulnerability and BERsys at higher clock frequencies, a trend attributed to temporal masking and throughput effects. Cross-node SPICE characterization between 65 nm and 28 nm reveals a technology-dependent effect: for the same injected charge, the 28 nm process produces a shorter root-level pulse, which lowers the propagation probability relative to 65 nm and shifts the optimal clock-tree partition. These findings underscore the framework’s key innovations: a technology-independent, early-stage VF for ranking critical clock nets; a clock-tree SER model calibrated by measured propagation probabilities; an ECO loop that converts VF insights into concrete hardening actions; and a fully reproducible open-source implementation. The paper’s scope is architectural and pre-layout, with extensions to broader circuit classes and a full electrical analysis outlined for future work.

In this study a new approach for skew compensation in energy recovery clock distribution networks is introduced by manipulating the operating speed of the flip-flops. The STMicroelectronics 90 nm technology allows the use of devices with different threshold voltages, namely: high threshold voltage (HVT), standard threshold voltage (SVT) and low threshold voltage (LVT). Three types of flip-flops of equal input load: fast , standard and slow are used. Timing parameters of the flip-flops are adjusted by manipulating the switching threshold of the clock port of the flip-flops. A fast/slow flip-flop has a shorter/longer T DQ delay, compared with a standard flip-flop for the same setup time (T DCLK ). Distributing flip-flops according to their delay requirements would reduce the effect of the clock's skew on the outputs of sequentially adjacent flip-flops. Owing to the slow rise time of the sinusoidal clock signal used in energy recovery clock distribution networks compared to the conventional square-wave clock, the skew that can be compensated for in energy recovery clock distribution networks using this approach would be much higher than in square-wave clock distribution networks. This approach increases the skew bounds required by algorithms to balance the skew in the clock tree leading to reduced design complexity. Theoretical analysis and simulation results using STMicroelectronics 90 nm technology at a clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% 1of the clock period can be compensated for in the example used. In addition, constructing clock trees using the skew slack provided in the proposed technique in a new modified differed merge embedding (DME) algorithm on five benchmarks have shown that the proposed technique enables an average reduction of 11.5% in total wire length and 53.2% reduction in the number of wire elongations. Balancing the skew in the clock tree using buffers was not considered here since inserting a buffer in the clock's path eliminates the energy recovery property. As an example of illustrating the proposed methodology, the authors have used the Elmore delay model with a selected energy recovery flip-flop to verify the practicality of the proposed scheme. Better results can be obtained by using different flip-flops. The method can generally be applied to energy recovery or square-wave clocking if different flip-flops of various speeds are used.

Macroblock pin assignment and routing are important tasks in physical design. Existing algorithms for these problems can be classified into two categories: 1) a two-step approach where pin assignment is followed by routing and 2) a net-by-net approach where pin assignment and routing for a single net are performed simultaneously. However, none of the existing algorithms is "exact" in the sense that they may fail to route all of the nets even though a feasible solution exists. This remains to be true even if only two-pin nets with fixed pins between two blocks are concerned. In this paper, we consider the problem of two-pin net connections from one macroblock to all of the other blocks, and present the first polynomial-time exact algorithm for simultaneous pin assignment and routing for all of the two-pin nets between one block (source block) and all of the other blocks. In addition to finding a feasible solution whenever one exists, it guarantees to find a pin-assignment/routing solution with minimum cost /spl alpha//spl middot/W+/spl beta//spl middot/V, where W is the total wire length and V is the total number of vias. Our algorithm has various applications. 1) It is suitable in engineering change order (ECO) situations where the existing solution is modified incrementally. 2) Given any pin assignment and routing solution obtained by any existing method, our algorithm can be used to increase the number of routed nets and reduce the routing cost. Furthermore, it provides an efficient algorithm for the pin assignment and routing problem of all of the blocks. The method is applicable to both global and detailed routing with arbitrary routing obstacles on multiple layers. Experimental results demonstrate its efficiency and effectiveness.

Functional Engineering Change Order (ECO) is necessary for logic rectification at late design stages. Existing works mainly focus on identifying a minimal logic difference between the original netlist and the revised netlist, which is called a patch. The patch is then implemented by technology mapping using spare cells. However, there may be insufficient spare cells around the physical location of the patch, or the wires connecting spare cells are too long, thus causing timing violations and routing congestion. In this paper, we propose a resource-aware functional patch generation approach by gate count and wiring cost estimations. In particular, we estimate the number of spare cells required by a patch and define a cost of wire length on it, which considers the physical location of the patch and a set of nearby spare cells. As a result, the patch with minimal wiring cost instead of minimal size is produced. The experiments are conducted on nine industrial testcases. These testcases reflect real problems faced by designers, and the results show our method is promising.

Macro-block pin assignment and routing are important tasks in physical design planning. Existing algorithms for these problems can be classified into two categories: 1) a two-step approach where pin assignment is followed by routing, and 2) a net-by-net approach where pin assignment and routing for a single net are performed simultaneously. None of the existing algorithms is in the sense that the algorithm may fail to route all nets even though a feasible solution exists. This remains to be true even if only 2-pin nets between two blocks are concerned. In this paper, we present the first polynomial-time exact algorithm for simultaneous pin assignment and routing for 2-pin nets from one block (source block) to all other blocks. In addition to finding a feasible solution whenever one exists, it guarantees to find a pin-assignment/routing solution with minimum cost α · W + β · V, where W is the total wirelength and V is the total number of vias. Our algorithm has various applications: 1) It is suitable in ECO (Engineering Change Order) situations where a designer wants to incrementally modify the existing solution instead of redoing everything after a design change. 2) Given any pin assignment and routing solution obtained by any existing method, our algorithm can be used to increase the number of routed nets and reduce the routing cost. Furthermore, it provides an efficient algorithm for the pin assignment and routing problem of all blocks. The method is applicable to both global and detailed routing with arbitrary routing obstacles on multiple layers. Experimental results demonstrate its efficiency and effectiveness.

As the layout of standard cells is becoming dense, accessing pins is much harder in detailed routing. The conventional solutions to resolving the pin access issue are to attempt cell flipping, cell shifting, cell swapping, and/or cell dilating in the placement optimization stage, expecting to acquire high pin accessibility. However, those solutions do not guarantee close-to-100% pin accessibility to ensure safe manual fixing afterward in the routing stage. Furthermore, there is no easy and effective methodology to fix the inaccessibility in the detailed routing stage as yet. This work addresses the problem of fixing the inaccessibility in the detailed routing stage. Precisely, (1) we produce, for each type of cell, multiple layouts with diverse pin locations and access points by modifying the core engines i.e., gate poly ordering and middle-of-line dummy insertion in the flow of design-technology co-optimization based automatic cell layout generation. Then, (2) we propose a systematic method to make use of those layouts to fix the routing failures caused by pin inaccessibility in the ECO (Engineering Change Order) routing stage. Experimental results demonstrate that our proposed cell layout diversification and replacement approach can fix metal-2 shorts by 93.22% in the ECO routing stage.

Among double patterning techniques, Self-aligned double patterning (SADP) has the advantage of good mask overlay control, which has made SADP a popular double patterning method for sub-32nm technology nodes. However, SADP process places several limitations on design flexibility. This work exploits an alternative post routing approach that has the flexibility to resolve lithography violations without the overhead of repeated rule checking. In addition, it allows for successive refinement in the definition of lithographic violations as the process node matures, and implementation of fixes as localized ECO (Engineering Change Order) operations without needing to reroute the complete design.