Closed-Form FIR Filter Design with Accurately Controllable Cut-Off Frequency

Digital filters play a central role in modern Digital Signal Processing (DSP) systems. Finite Impulse Response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

Digital filters play a central role in modern digital signal processing (DSP) systems. Finite impulse response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

Background/Objectives: FIR filters play a vital role in signal processing applications. This research work presents a low power and high speed efficient buffer based Distributed Algorithms and it is analyzed with Electro Cardio Gram (ECG) signal Finite Impulse Response (FIR) filter design. Methods/Statistical Analysis: The proposed FIR filter is designed using buffer based DA and it is simulated and synthesized using Cadence digital labs. This is compared with different architectures such as conventional DA, separated look up table DA and LUT less DA. Findings: Synthesis report shows that the proposed design has 52% less power dissipation compared with the conventional DA, 21% reduction in delay with separated Look Up Table (LUT) DA and 8% reduction in area with LUT less DA. Conclusion/Improvements: Presently this method is applied for ECG signal input with 16-tap FIR filter. This can be extended for higher order filters to achieve better performance.

WITHDRAWN: An Optimistic Design of 16-Tap FIR Filter with Radix-4 Booth Multiplier Using Improved Booth Recoding Algorithm

Chapter 2 - Design and Implementation of Digital FIR Filters

An Finite Impulse Response (FIR) filter is a widely used digital filter technology whose impulse response has a finite duration. An FIR filter is usually favored for many reasons such as easy to design, easy to implement on a variety of system architectures. An FIR filter can be easily designed with a linear phase response and its output is more predictable since it doesn't have feedback components. There are both engineer and mathematical methods for designing an FIR filter so that machine learning doesn't play an important role in the FIR filter design. In this paper, we present an alternative to traditional filter design methods to direct learn the FIR filter coefficients from input data with machine learning algorithm. With the proposed algorithm, we can easily design an FIR filter from the input data mixed with designed all spectrum noise signal. To show the capability of this algorithm, an example application of suppressing background music from speech or vice versa is demonstrated in this paper. Despite that the music and speech have a lot of overlap in their spectrum, the filter designed by our algorithm can successfully suppress music or speech in a mixture of music and speech signals.

PurposeTraditionally, each time a new design for a finite impulse response (FIR) filter is required, a new algorithm has to be developed specially for the FIR filter. Furthermore, corresponding hardware architecture must be designed specially to meet the requirement of the FIR specifications. The purpose of this paper is to propose an arithmetic logic unit (ALU)‐based universal FIR filter suitable for realization in field programmable gate arrays (FPGA), where various FIR filters can be implemented just by programming instructions in the ROM with identical hardware architecture.Design/methodology/approachRather than multiplier‐accumulator‐based architecture for conventional FIR, the proposed ALU architecture implements the FIR functions by using accumulators and shift‐registers controlled by the instructions of ROM. Furthermore, time division multiplexing access (TDMA) technique is employed to reduce the chip size. In addition, the proposed FIR architecture is verified in a SOC hardware and/or software co‐emulation system.FindingsAn ALU‐based universal FIR filter suitable for realization in FPGA is designed and verified in a SOC hardware/software co‐emulation system with example of a 64‐tap FIR filter design.Originality/valueA software‐based design method as well as TDMA scheme for the ALU‐based FIR filter are introduced, making FIR filter architecture universal, programmable, and consuming less FPGA resources.

High computational complexity is a major problem encountered in the optimal design of two-dimensional (2-D) finite impulse response (FIR) filters. In this paper, we present an iterative matrix solution with very low complexity to the weighted least square (WLS) design of 2-D quadrantally symmetric FIR filters with two-valued weighting functions. Firstly, a necessary and sufficient condition for the WLS design of 2-D quadrantally symmetric filters with general nonnegative weighting functions is obtained. Then, based on this optimality condition, a novel iterative algorithm is derived for the WLS design problem with a two-valued weighting function. Because the filter parameters are arranged in their natural 2-D form and the transition band is not sampled, the computation amount of the proposed algorithm is reduced significantly, especially for high-order filters. The exponential convergence of the algorithm is established, and its computational complexity is estimated. Design examples demonstrating the convergence rate and solution accuracy of the algorithm, as well as the relation between the iteration number of the algorithm and the size and transition-band width of the filter are given.

This paper presents a novel approach for the design of two-dimensional (2D) Finite Impulse Response (FIR) filters. The design of FIR filters is generally non-differentiable, multimodal and higher dimensional; especially for 2D filters. A large number of filter coefficients are optimized either using constrained or unconstrained optimization approach. Due to the large number of constraints, traditional design methods cannot produce optimal filters required for some crucial applications. This makes meta-heuristic algorithms as good alternatives for addressing such constraints more efficiently. In order to improve the performance of 2D filters, we propose an Accelerated Artificial Bee Colony algorithm, termed as AABC algorithm. The earlier reported ABC based methods perform the modification of a single parameter of the solution in each cycle. But in this proposed AABC algorithm, we have adopted multiple parameters change of search equation at each step. This in turn improves the convergence speed of the algorithm by three times than the classical ABC algorithm and two times with respect to recently developed CABC method. In order to achieve better exploration behaviour of abandoned bees, we have also introduced a change during the initialization strategy of scout bees in the proposed AABC algorithm. The efficiency and robustness of the proposed algorithm are demonstrated by comparing its performance with classical Genetic Algorithm (GA), Particle Swarm Optimization , ABC and CABC methods.

In recent years, several approaches have been investigated to obtain multiplier-free realizations of digital filters. One approach makes use of periodically time-varying (PTV) structures. The idea is to distribute the computation in time and in space. Distribution in time provides reuse of the same hardware by means of PTV coefficients. Distribution in space increases the number of coefficients but simplifies the values of the coefficients. Computation distribution is based on radix-r number representation, and it can be carried out to the extent that each computation involves a simple coefficient that can be realized using only addition and shift (no hardware multiplier). Previous PTV realizations could not exploit the coefficient symmetry of finite impulse response (FIR) filters to reduce the number of coefficients. This paper proposes design and realizations of FIR filters with punctured radix-8 coefficients belonging to the septuple set {0, ±1, ±2, ±4), which can be implemented using only a shift operation without requiring any hardware multiplier. The realizations exploit the coefficient symmetry to reduce the hardware by about one-half. Due to a non-uniform grid of representation, we apply a modified Karmarkar's linear programming algorithm to find the optimum set of discrete coefficients that minimizes the weighted peak ripple error. Comparison with a conventional FIR filter with sum-of-powers-of-two (SOPOT) coefficients shows that the proposed filter is faster and uses less hardware than one with SOPOT coefficients. However, the punctured radix-8 system has a limit on the achievable ripple.

The paper presents the design and implementation of a high speed digital Finite Impulse Response (FIR) filter using unfolding transformation technique. FIR Filter has widespread applications in signal processing such as image processing, biomedical signal processing, high speed communication systems, noise elimination and many more. The speed of FIR filter can be improved with high speed vedic multiplier and with low propagation delay carry increment adder. In the proposed design, the FIR filter is unfolded by a factor 3 which results in scheduling the filter to a smaller iteration period and along with this throughput of the filter also increases. The propagation delay is reduced to almost three times in FIR filter by using faster adder, high speed multiplier and unfolding transformation technique. We have synthesized the proposed design on Xilinx ISE 14.7 with Virtex IV FPGA family. The obtained results also confirm the faster performance of the FIR filter.

SummaryThis work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high‐performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high‐capacity hybrid (HC‐hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC‐180 nm and UMC‐65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns.

The design of finite impulse response (FIR) filters in one or two-dimensions can be performed with good computational efficiency using weighted least square (WLS) design. This paper presents an improved WLS technique for the design of 2-D FIR filters. We introduce an updating desired frequency response, which implicitly includes the weighting function such that the sum of weighted square errors to be minimized can be represented in a 2-D matrix form. This makes it possible to keep all filter parameters in their natural 2-D form, thereby reducing the computational complexity from O(N/sup 6/) to O(N/sup 3/). It is confirmed through design examples that our approach is computationally efficient and leads to nearly optimal approximations.

In this communication, one novel attempt has been made towards the design of minimum-phase finite impulse response (FIR) filter using one evolutionary computation technique, named differential evolution (DE) algorithm. Mean square error (MSE) between the frequency samples of the ideal filter and the designed filter in the pass-band and stop-band region and the minimum average error (MAE) between the frequency samples in the transition-band region had been considered for the formulation of the objective function in the optimization process. Performance of the optimization technique has been monitored in terms of convergence characteristics for four different orders of FIR filter under consideration. Robustness of our proposition has been firmly established in the sense that the proposed algorithm can be suitably tuned for the design of low-pass, high-pass or band-pass FIR filter of different specifications. Supremacy of the proposed algorithm over other existing techniques for the design of minimum-phase FIR filter has been substantiated by means of frequency response and pole-zero diagrams.

In Digital wireless communication system Finite Impulse Response (FIR) filter is used fundamentally pipelined as well as support Multiplication with Accumulation scheme (MAC) that results in important save of calculation. Efficient area along with delay recognition of great order FIR filters for update applications have been achieved by the opportunity of recognition of block FIR filter in transpose form organization. The projected transpose form block filter of update applications are developed by a general carry select adder based architecture. Secured digital FIR filter block is implemented by a pepped-up design using the MAC scheme. Booth multiplier has been used in MAC scheme. The proposed method has less area also delay than conventional filter.