CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors

Stroke is a leading cause of disability and impaired arm function is a common consequence. Constraint-induced movement treatment is a technique used to increase weak arm use and to decrease motor deficits resulting from stroke. Eleven stroke survivors participated in a constraint-induced movement treatment protocol of 3 ½ hours of treatment per day for 8 days. Participants experienced significantly increased use of the weak arm in daily activities, which was measured by the Motor Activity Log, and a trend toward improved coordination in the weak arm, which was measured by the Wolf Motor Function Test. Participants did not report significant improvements in average performance or satisfaction in self-identified occupational performance problems. When these problems were analyzed individually, no significant differences were seen immediately post-treatment. However, significant improvements were seen for satisfaction at 4 to 6 months post-treatment. The occupational performance problems identified by the participants were equally divided between problems related to hand use and problems not related to hand use. Approximately half of the non-hand use problems involved endurance. Although participants in this study did make improvements in arm use and coordination, they did not identify improvements in average occupational performance or satisfaction as an outcome of constraint-induced movement treatment.

Thermal management of DRAM memory has become a critical issue for server systems. We have done, to our best knowledge, the first study of software thermal management for memory subsystem on real machines. Two recently proposed DTM (Dynamic Thermal Management) policies have been improved and implemented in Linux OS and evaluated on two multicore servers, a Dell PowerEdge 1950 server and a customized Intel SR1500AL server testbed. The experimental results first confirm that a system-level memory DTM policy may significantly improve system performance and power efficiency, compared with existing memory bandwidth throttling scheme. A policy called DTM-ACG (Adaptive Core Gating) shows performance improvement comparable to that reported previously. The average performance improvements are 13.3% and 7.2% on the PowerEdge 1950 and the SR1500AL (vs. 16.3% from the previous simulation-based study), respectively. We also have surprising findings that reveal the weakness of the previous study: the CPU heat dissipation and its impact on DRAM memories, which were ignored, are significant factors. We have observed that the second policy, called DTM-CDVFS (Coordinated Dynamic Voltage and Frequency Scaling), has much better performance than previously reported for this reason. The average improvements are 10.8% and 15.3% on the two machines (vs. 3.4% from the previous study), respectively. It also significantly reduces the processor power by 15.5% and energy by 22.7% on average.

Due to the exceptional benefits of cloud computing, it has magnetized IT leaders and entrepreneurs at all levels. The cloud's popularity is attributed to various technologies like the Internet of Things (IoT), mobile computing, Fog, etc. Scheduling in cloud computing is still a challenging issue due to its NP-Hard nature. In recent years, many techniques have been proposed for optimal scheduling that can subsequently improve efficient Quality of Service (QoS). This paper has developed and analysed a novel Sailfish Optimization-based Scheduling Algorithm. SOSA is implemented on 2 data-sets; a real-world data-set from NASA workload, and a randomly generated data-set. SOSA exhibited 13.71 and 7.81 % average performance improvement in makespan compared to GA and PSO and 11.30 and 30.78 % average improvement in execution cost compared to GA and PSO.
 HIGHLIGHTS
 
 Scheduling in Cloud computing has NP -Hard Problem nature that may degrades Quality of Service to users
 A Novel Sailfish optimization based scheduling algorithm (SOSA) technique is proposed to increase Quality of Service in terms of Makespan and Execution Cost
 Simulation has been performed in CloudSim on NASA workload and synthetic dataset
 Proposed SOSA techniques proves to be more effective to provide Quality of Service and proves to be more significant as compared to GA and PSO

In order to speedup image processing in embedded environment, we construct a parallel processing system of images. The parallel processing system includes a parallel hardware, a new defined language for parallel image processing and a set of software tools. From the view of high performance, low power dissipation and the characteristics of image processing, we construct a SIMD coprocessor as an image processing accelerator. Using a RISC host processor manages the whole system. The SIMD processor is scalable. We also define a new language which is extended from standard C. A new data type and a new keyword kernel are added to the language to explicitly describe parallelism. For the new hardware and language of parallel image processing, we also research software tools for this parallel system. The software tools maps programs to code that runs on the new hardware. For example develop a scheduler to transfer stream data between memories and register files. From the analysis we found that the parallel image processing system can not only match image applications' characteristics but also easy to implement by using VLSI technology. With new language and software tools supporting, an embedded real-time parallel image processing system becomes available for programmers.

The instruction set architecture of vector processors operates on vectors stored in the vector register file which needs to handle several concurrent accesses by functional units with multiple ports. When the vector processor is running with high utilization, access conflicts become a major source of performance degradation. With a software model of a vector processor, we take a deep dive into the runtime impact of conflicts and their characteristics, and on ways to manage them, i.e., avoidance, resolution, and mitigation. For conflict avoidance, we study the existing approaches of banking with different static bank layouts and propose a dynamic bank layout to overcome their shortcomings. Our approach assigns newly written registers a temporarily unique starting bank. For conflict resolution, we compare different arbitration algorithms and optimize round-robin arbitration for mixed-width arithmetics by prioritizing wide operands. For conflict mitigation, operand queues of varying depths are studied. Our inventions are likely to increase the area efficiency of vector processors, either because they allow to use shallower operand queues while keeping the same performance, or reduce the area even further by using less banks, albeit at a performance impairment of 10% or less. The insights of the study can further be applied to other shared memory systems.

SIMD processors are increasingly used in embedded systems for multi-media applications because of their area- and energy-efficiency. Communication between the processing elements (PEs) in an SIMD processor has remained a cause of inefficiency however; the SIMD concept prescribes that all PEs communicate in the same clock cycle. Existing SIMD architectures solve this problem either by multi-hop communication (causing cycle overhead), or by a fully connected communication network (causing area overhead). To solve the communication bottleneck, we propose a reconfigurable SIMD architecture (RC-SIMD) with a set of delay-lines in the instruction bus, distributing the accesses to the communication network over time. We can (re-) configure the size and number of delay-lines, a specific configuration representing a trade-off between the number of clock cycles and the length of a clock period. Reconfiguration time is typically much less than 1% of the execution time of an algorithm, and the extra configuration hardware is less than 2%. Experiments show that our reconfigurable architecture achieves (on average) more than 10% performance improvement over a non-reconfigurable architecture.

Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed microarchitectures in which the compiler forms dataflow graphs that specify how the microarchitecture maps instructions onto a distributed execution substrate. This paper describes a compiler scheduling algorithm called spatial path scheduling that factors in previously fixed locations - called anchor points - for each placement. This algorithm extends easily to different spatial topologies. We augment this basic algorithm with three heuristics: (1) local and global ALU and network link contention modeling, (2) global critical path estimates, and (3) dependence chain path reservation. We use simulated annealing to explore possible performance improvements and to motivate the augmented heuristics and their weighting functions. We show that the spatial path scheduling algorithm augmented with these three heuristics achieves a 21% average performance improvement over the best prior algorithm and comes within an average of 5% of the annealed performance for our benchmarks.

In this work, the creation of a dataset labeled in a pixel-wise manner for the uncommon domain of stain detection on patterned laundry is described. The unique properties of images in this dataset—stains are small and sometimes occur in large amounts—led to the creation of noisy labels. Indeed, the training of a fully convolutional neural network for salient object detection with this dataset revealed that the model predicts stains missed by human labelers. Thus, the reduction in label noise by adding overlooked regions with the help of the model’s predictions is examined in two different experiments. In the model-assisted labeling experiment, a simulation is ran where a human selects correct regions from the predictions. In the self-training experiment, regions of high certainty are automatically selected from the predictions. Re-training the model with the revised labels shows that model-assisted labeling leads to an average improvement in performance by 8.52%. In contrast, with self-training, the performance increase is generally lower (2.58% on average) and a decrease is even possible since regions of high certainty are often false positives.

Aspect category detection (ACD) is a basic task in sentiment analysis that aims to identify the specific aspect categories discussed in reviews. In the case of limited label resources, prompt-based models have shown promise in few-shot ACD. However, their current limitations lie in the manual selection or reliance on external knowledge for obtaining the verbalizer, a critical component of prompt learning that maps predicted words to final categories. To solve these issues, we propose an ACD method to automatically build the verbalizer in prompt learning. Our approach leverages the semantic expansion of category labels as prompts to automatically acquire initial verbalizer tokens. Additionally, we introduce an indicator mechanism for auto-verbalizer filtering to obtain reasonable verbalizer words and improve the predicting aspect category reliability of the method. In zero-shot task, our model exhibits an average performance improvement of 7.5% over the second-best model across four ACD datasets. For the other three few-shot tasks, the average performance improvement over the second-best model is approximately 2%. Notably, our method demonstrates effectiveness, particularly in handling general or miscellaneous category aspects.

Due to the prevalence of music performance anxiety and the emergence of new biofeedback technologies used to decrease anxiety, student musicians were recruited to participate in an experimental repeated-measures study to identify effects of heart rate variability coherence biofeedback training and emotional self-regulation techniques on music performance anxiety and music performance. Fourteen students were assigned randomly to a treatment or control group following a 5-minute unaccompanied baseline performance. Treatment group participants received 4–5 heart rate variability training sessions of 30–50 minutes each. Training included bibliotherapy, computerized heart rate variability biofeedback training, emotional regulation exercises, and use of a portable heart rate variability training device. Measures included the State-Trait Anxiety Inventory, Performance Anxiety Inventory, Flow State Scale, average heart rate, and heart rate variability. Quade's rank-transformed analysis of covariance was used to evaluate treatment and no-treatment group comparisons. Combined music performance anxiety scores showed statistically significant improvement at a p = .05 level with a large effect size of ηp2 = .320. State anxiety measurement showed a large effect size of ηp2 = .291. The Performance Anxiety Inventory showed a large effect size of ηp2 = .149. Heart rate showed a large effect size of ηp2 = .143. Heart rate variability showed statistical significance at p = .001 level and a large effect size of ηp2 = .698. The treatment group average subjective decrease in music performance anxiety was 71%, and the treatment group average subjective improvement in performance was 62%. This study demonstrated statistical and practical/clinical significance of a relatively quick and inexpensive biofeedback training that had a large effect on decreasing mental, emotional, and physiological aspects of music performance anxiety and subjective improvement of performance for university students.

The demise of Dennard’s scaling has created both power and utilization wall challenges for computer systems. As transistors operating in the near-threshold region are able to obtain flexible trade-offs between power and performance, it is regarded as an alternative solution to the scaling challenge. A reduction in supply voltage will nevertheless generate significant reliability challenges, while maintaining an error-free system that generates high costs in both performance and energy consumption. The main purpose of research on computer architecture has therefore shifted from performance improvement to complex multi-objective optimization. In this paper, we propose a three-dimensional optimization approach which can effectively identify the best system configuration to establish a balance among performance, energy, and reliability. We use a dynamic programming algorithm to determine the proper voltage and approximate level based on three predictors: system performance, energy consumption, and output quality. We propose an output quality predictor which uses a hardware/software co-design fault injection platform to evaluate the impact of the error on output quality under near-threshold computing (NTC). Evaluation results demonstrate that our approach can lead to a 28% improvement in output quality with a 10% drop in overall energy efficiency; this translates to an approximately 20% average improvement in accuracy, power, and performance.

Cochlear Implantation in Inner Ear Malformations: Systematic Review of Speech Perception Outcomes and Intraoperative Findings.

Outdoor air ventilation rates vary considerably between and within buildings, and may be too low in some spaces. The purpose of this study was to evaluate the potential work performance benefits of increased ventilation. We analyzed the literature relating work performance with ventilation rate and employed statistical analyses with weighting factors to combine the results of different studies. The studies included in the review assessed performance of various tasks in laboratory experiments and measured performance at work in real buildings. Almost all studies found increases in performance with higher ventilation rates. The studies indicated typically a 1-3% improvement in average performance per 10 l/s-person increase in outdoor air ventilation rate. The performance increase per unit increase in ventilation was bigger with ventilation rates below 20 l/s-person and almost negligible with ventilation rates over 45 l/s-person. The performance increase was statistically significant with increased ventilation rates up to 15 l/s-person with 95% CI and up to 17 l/s-person with 90% CI. Practical Implications We have demonstrated a quantitative relationship between work performance and ventilation within a wide range of ventilation rates. The model shows a continuous increase in performance per unit increase in ventilation rate from 6.5 l/s-person to 65 l/s-person. The increase is statistically significant up to 15 l/s-person. This relationship has a high level of uncertainty; however, use of this relationship in ventilation design and feasibility studies may be preferable to the current practice, which ignores the relationship between ventilation and productivity.

Register files are a key data storage unit that impacts instruction throughput for graphics processing units (GPUs). Typically, GPU register files are quite large to accommodate many concurrent threads and are implemented using the same SRAM technology as the on-chip cache. We propose contextrf, a new register file architecture that efficiently leverages register files with nonuniform access characteristics, including hybrid SRAM/DRAM (S/D) and spintronic domain-wall memories (DWMs). Contextrf allows greater-capacity register files to be implemented in the same area within the GPU, with reduced power consumption. We also propose contextPreRF, a hardware preswitch scheme to hide switching delays—as soon as a register request is queued, the nonuniform access memories containing the corresponding register are sent a preemptive switch request. Thus, our scheme transparently hides the penalties of switching between register contexts. After replacing the register file SRAM with S/D, we can reduce energy by 37%, with a 1.4% average performance drop. Employing DWM, we reduce register file energy by 74%, with a 0.4% average performance penalty. For the denser DWM, we model converting the saved area into additional registers, cache, and shared memory—this improves performance by 13.5% over the baseline SRAM register file.

Modern General Purpose Graphic Processing Unit (GPGPU) demands a large Register File (RF), which is typically organized into multiple banks to support the massive parallelism. Although heavy banking benefits RF throughput, its associated area and energy costs with diminishing performance gains greatly limit future RF s-caling. In this paper, we propose an improved RF design with a bank stealing technique, which enables a high RF throughput with compact area. By deeply investigating the GPGPU microarchitecture, we identify the deficiency in the state-of-the-art RF designs as the bank conflict problem, while the majority of conflicts can be eliminated leveraging the fact that the highly-banked RF oftentimes experiences under-utilization. This is especially true in GPGPU where multiple ready warps are available at the scheduling stage with their operands to be wisely coordinated. Our lightweight bank stealing technique can opportunistically fill the idle banks for better operand service, and the average GPGPU performance can be improved under smaller energy budget with significant area saving, which makes it promising for sustainable RF scaling.