Co-deinterlacing between video decoder and video post-processor

We have implemented a so/bvare on(v MPEG-2 Azidio Video Decode (MAVD) system on the Cradle MDSP architectlire arid we highlight the siritobilip of MDSP' architectrire to e.rpluit the data, algorithinic, and pipeline parallelization q/fered hv Video processing algoritlnw like the MPEG2 Video ./or real-time perJiirniance and efficient partitioning a/ Systeiir. Audio and Video Proces.sing 017 a single chip nniltiprocessor. Most e.xisting implementations extract either data or pipeline paralleli.sm along with Instmction Level Paralleli.sm (ILP) in their implementations. We disciics the design of MP@ML MPEG2 video decoding system and MPEG-2 Stereo Decode Svsten? on this shored memon, MDSP plulfbrm. We also highlight how tl7e processor scalahilit?, is exploited as part of the design on this architectirre. Althaiigh simiiltaneous audio-video decode on general-pirrpose processors provides ,/le.rihilip, they are not cost-effective. Most of the media prucesu0r.s exploit hardware acceleration in part or Jirll to alleviate the high-thro~ighprit demands pnt hv these algorithins; thewhy making tl7em inJlerih1e Jar other applications. With the fle.rihility ofired IJV the Cradle platform we cozrld design a video decoder that coiild scale Jiom fbsr MSP.s (Media Stream Proce.ssor that is a clrister ufone RISC arid hvo DSP processors) to eight MSPs and hrrild a single-chip solntian inchiding the 10 interfaces ,for, videa/aridio output. TI7e s,vstem l7a.s heen tested on Cradle's internal CRA20.03 evahiation hoard. Specific contributions inclrrde the mdtiple VLD algorithm and other heiiri.stic approaches like ea!-ly- termination IDCTJbrfast video decoding.

A low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/AVC to reduce silicon area. Three low-power techniques are proposed. First, a domain-pipelined scalability (DPS) technique is used to optimize the pipelined structure according to the number of processing cycles. Second, bandwidth scalability is implemented via a line-pixel-lookahead (LPL) scheme to improve the external bandwidth and reduce the internal memory size, leading to 51% of memory power reduction compared to a conventional design. Third, low-power motion compensation and deblocking filter are designed to reduce the operating frequency without degrading system performance. A test chip is fabricated in a 0.18mum one-poly six-metal CMOS technology with an area of 15.21 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . For mobile applications, H.264/AVC and MPEG-2 video decoding of quarter-common intermediate format (QCIF) sequences at 15 frames per second are achieved at 1.15 MHz clock frequency with power dissipation of 125 muW and 108 muW, respectively, at 1V supply voltage

In this paper, we introduce a direction-oriented covariance-based adaptive deinterlacing (CAD) method. The conventional CAD method preserves edge direction; however, it does not consider the local edge direction, which makes it unsuitable for real-time applications. The proposed method only utilizes the neighbor pixels aligned in the local edge direction to obtain optimal coefficients, with less processing time than the aforementioned CAD. First, the local edge direction is determined using the modified edge-based line average method. Then, based on direction-oriented geometric duality, the optimal interpolation coefficients for the neighbor pixels in the corresponding direction are estimated using the Wiener filter. Furthermore, we present inverse-free least squares approximations using orthogonal-triangular decomposition based on the Gram-Schmidt process. This technique's performance improves as the size of the image becomes larger. The experimental results prove that the proposed method provides a significant improvement over other deinterlacing methods.

Based on the analysis of conventional deinterlacing methods, a new motion adaptive deinterlacing method is proposed. In this paper, we improve three aspects of the conventional motion adaptive method. Firstly, we add a FIR filter to the motion detection part, which not only avoids the wrong detecting of moving objects but also reduces the noises effectively. Secondly, according to the fact, that human eyes are less sensitive to lighter or darker area than gray area, a threshold adaptive method is introduced, which enhanced the subjective quality of deinterlacing. Thirdly, we adopted different interpolation methods for different pixels, which improved the deinterlacing quality of motionless videos. The simulation results show that our proposed deinterlacing method can achieve higher PSNR (peak signal noise ratio) than that of previous studies and can also attain better quality of subjective view.

MPEG video decoding algorithm has been embedded into many consumer electronic products. In this paper, we demonstrate that the completion ratio (CR) does not represent well the quality of presentation (QoP) of MPEG video. We then propose a new QoP metric, which 1) is based on frame completion ratio but 2) differentiates firm and soft deadlines and also 3) considers the frame dependency. We show that, on a set of simulates MPEG movies; the proposed QoP metric measures the QoP of the movies much better than completion ratio. We then present a set of online scheduling algorithms that enhance QoP significantly, particularly for overloaded systems.

This paper gives a description of our real-time software MPEG-4 video decoder. The performance of the decoder and the fast algorithms used for real-time decoding are discussed. Our techniques used to speed up four computationally intensive modules, inverse discrete cosine transform, context-based arithmetic decoding, padding, and variable length decoding, are also presented in this paper. Our decoding speed is improved so that software real-time video decoding is possible.

The objective of this paper is to introduce the Stochastic Automata Networks (SANs) as an effective formalism for application modeling in system-level analysis. More precisely we present a methodology for application modeling for system-level power/performance analysis that can help the designer to select the right platform and implement a set of target multimedia applications. We also show that, under various input traces, the steady-state behavior of the application itself is characterized by very different 'clusterings' of the probability distributions. Having this information available, not only helps to avoid lengthy profiling simulations for predicting power and performance figures, but also enables efficient mappings of the applications onto a chosen platform. We illustrate the benefits of our methodology using the MPEG-2 video decoder as the driver application.

Motivated by data value locality and quality tolerance present in multimedia applications, we propose a new micro-architecture, region-level approximate computation buffer (RACB), to reduce power consumption in such applications. The proposed RACB relaxes the exact matching into partial and approximate tag matching and applies it to regions of code in a program, thereby allowing for aggressive computation/execution reduction, in addition to reductions in memory accesses and pipeline activities. Our experiments demonstrate that a 64-entry RACB can yield up to 70% of region-level execution reduction without noticeable quality degradation in MPEG-2 video decoding, corresponding to 55.9% of system power savings with respect to the regions.

Frequency-voltage cooperative power control (FVC) is considered a powerful method to reduce the power consumption of a program, because it utilizes the information of software loads dynamically. The authors first show through a mathematical analysis that FVC with only two frequency-voltage sets is sufficient for current low-Vdd CPU chips. Then we show an experimental result that FVC feedback control on an MPEG-4 video decoder can reduce the power to one-fourth.

This paper investigates the problem of error propagation in MPEG-4 video decoding when the DCT coefficients have been damaged. The problem is unique since the Intra DC/AC prediction tool adopted by the standard allows for coefficients to be predicted from both the horizontal and vertical directions. Although the standard offers a variety of error resilience techniques to prevent such errors from propagating, they are encoder dependent and one cannot guarantee that suitable encoding parameters have been chosen. Therefore, we propose a robust decoding method that reduces the propagation of such errors.

Digital video decoding is a typical data-intensive video processing application. Currently, high throughput and real time processing are the fundamental demands of performance for video processing systems. With the development of various video standards, multi-standard applications have become another key feature. Thus, the high performance, low area cost and low power consumption make up the most important design targets when realizing video processing chips. Reconfigurable hardware architectures have been reviewed in this paper, which could meet the above requirements for multi-standard video decoders. Traditional reconfiguration methods usually decrease area cost by reconfiguring the interconnections among function units. A relatively new approach is dynamic reconfiguration, which could reconfigure hardware resources at runtime. Recently, a new method called Reconfigurable Video Coding (RVC) has come up, which is a library-based method to design a reconfigurable system for multi-standard video decoders. An overview of the methodologies for reconfigurable video processing system is shown in the paper, as well as case studies, which demonstrate the effectiveness of the design flow. The article presents some promising patents on design of reconfigurable architectures for multi-standards video decoder.

Digital video decoding, enabled by the MPEG-2 video standard, is an important future application for embedded systems, particularly personal digital assistants and other information appliances. Many such systems require portability and wireless communication capabilities, and thus face severe limitations in size and power consumption. This places a premium on integration and efficiency, and favors software solutions for video functionality over specialized hardware. Apart from computation, an equally important problem in video decoding is the data bandwidth and the need to insure adequate data supply. MPEG data sets are very large, and generate significant amounts of excess memory traffic for standard data caches, up to 100 times the amount required for decoding. Yet MPEG data has locality which caches can exploit if properly optimized, providing fast, flexible, and automatic data supply. We propose a set of enhancements which target the specific needs of the heterogeneous types within the MPEG decoder working set. These optimizations significantly improve the efficiency of small caches, reducing cache-memory traffic by almost 70%, and can make an enhanced 4-kB cache perform better than a standard 1 MB cache. This performance improvement can enable high-resolution, full frame rate video playback in cheaper, smaller systems than would otherwise be possible.

This paper presents a low-complexity motion compensation (MC) aided motion adaptive (MA) de-interlacing method, aiming at effectively leveraging the fact human eyes are not sensitive to high spatial frequency with rapid motion. The basic idea is to enhance MA de-interlacing by applying MC de-interlacing to process slow-moving objects. Compared with conventional MC de-interlacing, the motion estimation only needs to search in a much smaller area and can adaptively switch between the same parity and opposite parity fields according to the motion vector. Simulation demonstrates that the proposed method only incurs less than 5% of computational complexity of general MC de-interlacing, and meanwhile can improve the PSNR by up to 10 dB compared with conventional MA methods. Its silicon cost and energy consumption are further evaluated by an ASIC design at 0.13 mum technology node.

A same-parity 4-field based motion adaptive deinterlacing algorithm combining with texture detection is presented in this paper. Comparing with the existing low-end deinterlacing algorithm, this method greatly improves image quality for both static and fast moving objects due to high motion detection accuracy. Its hardware architecture is also simpler than high-end deinterlacer architecture, e.g. motion estimation & compensation deinterlacer. Its FPGA implementation is also presented.

Motion-adaptive de-interlacing algorithm selects from inter-field and intra-field interpolations according to motion. Correct determination of motion information is essential for this purpose. Fine textures, having high local pixel variation, tend to cause false detection of motion. This paper proposed a texture detection mechanism utilizing multiresolution technique to improve the correctness of detection. A recursive 2-field algorithm is also proposed to reduce the memory cost in 4-field method. This algorithm provides better perceptual visual quality than other motion adaptive de-interlacing as shown by the experimental results.