Combined Distributed Shared-Buffered and Diagonally-Linked Mesh Topology for High-Performance Interconnect

Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation

Increase in the speed of processors has led to crucial role of communication in the performance of systems. As a result, routing is taken into consideration as one of the most important subjects of the Network on Chip architecture. Routing algorithms to deadlock avoidance prevent packets route completely based on network traffic condition by means of restricting the route of packets. This action leads to less performance especially in non-uniform traffic patterns. On the other hand True Fully Adoptive Routing algorithm provides routing of packets completely based on traffic condition. However, deadlock detection and recovery mechanisms are needed to handle deadlocks. Use of global bus beside NoC as a parallel supportive environment, provide platform to offer advantages of both features of bus and NoC. This bus is useful for broadcast and multicast operations, sending delay sensitive signals, system management and other services. In this research, we use this bus as an escaping path for deadlock recovery technique. According to simulation results, this bus is suitable platform for deadlock recovery technique.

56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology

Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater

5G network is an enhanced communication network, designed to converge the requirements of quality of service (QoS) parameters, data and capacity, by means of signals with high QoS and high-speed data rate. Several state-of-art technologies are involved to obtain the requirement of energy efficient communication system with increased number of users, devices, higher data rate with low latency. This paper presents a system which demonstrates the energy and spectral efficiency achieved for various number of nodes in a specific area. This study addresses the improvement in energy and spectral efficiency when the proposed algorithm is used. The proposed algorithm is a combination of swarm based artificial bee colony (ABC) algorithm with neural network. Experimental results have been carried out to observe the performance of QoS parameters such as bit error rate (BER), throughput, power consumption and mean square error (MSE). The maximum energy efficiency achieved is 34% and Spectral efficiency is 36%.

The design of very large-scale integrated circuits passes through many critical stages and challenges the advanced technology of nanometer CMOS technology. The major problem included in the existing process is the leakage current and reliability issues. Penta-magnetic tunnel junction (Penta-MTJ) hybrid with CMOS technology has many advantages in the VLSI strategy such as higher performance and low leakage current. The methodology of the proposed work includes the increase in the storage capacity with optimized power and speed using transmission gate logic and decrease in area and power in combinational and sequential circuits. The structure of Penta-MTJ includes the design of transmission gates to increase the speed with the minimum number of gates to reduce the area and power consumption. By decreasing the number of transistors in transmission gate logic, the power consumption was reduced to 12 and 18%. To overcome the sensing reliability issue, high sensing margin is proposed in the design circuit. With a 43.9 and 10.7% increase in energy delay product (EDP), the proposed approach reduces energy demand while incurring low area overhead.KeywordsPenta-magnetic tunnel junction (MTJ)Transmission gate logic (TGL)SpintronicsEnergy delay product

This thesis discusses the potential of CMOS based SiPMs, especially for TOF PET applications, in a systematic and comprehensive fashion. CMOS based SPADs are still need to be designed carefully to improve fill factor, TDCs be improved from the point of the area and power consumption, and the necessity of high voltage for SPADs be handled efficiently. Thus, this thesis also aims to design and integrate various circuits in the SiPM to realize the high integrations utilizing the biggest advantage of the CMOS technology.

A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as -21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 mm 2 .

In this paper, a low-power half-rate charge-steering echo cancellation hybrid circuit topology is proposed for full-duplex signaling over chip-to-chip interconnects. The proposed half-rate charge-steering hybrid topology has a very low power consumption compared to traditional current-mode and voltage-mode hybrid circuit topology implementations, thanks to the discrete nature of charge-steering hybrid topology avoiding direct current path between V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> and ground. The half-rate hybrid circuit topology has been implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The post-layout performance of the half-rate charge-steering hybrid including package parasitic has a differential received signal voltage swing of 0.8 V at 10 Gb/s data rate with a timing jitter of 10 ps over a FR4 PCB interconnect of length 20 cm. The total power consumption of the half-rate charge-steering hybrid is only 0.16 mW and its energy efficiency is 0.032 pJ/bit. The layout of the hybrid occupies an area of 0.0007 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A voltage reference is indispensable in Integrated Circuits. To improve the limited linear output voltage range and energy efficiency of a voltage reference, we innovatively propose a switched-capacitor-based programmable voltage reference scheme employing inverter-based OTAs to reduce the power consumption, simultaneously using a novel Correlated Level Shifting (CLS) technique (without active overhead) to enhance the OTA’s DC gain and integral gain. Experimented with SMIC 180 nm CMOS technology, a scheme-based voltage reference realizes a programable output voltage range from 266 to 995 mV at −30 to 120 °C, and the corresponding temperature coefficient (TC) ranges from 82.4 to 99.5 ppm/°C. The power consumption is 976 nW. Furthermore, comparative experiments and evaluations with other schemes have unequivocally verified the superiority of our proposed scheme, characterized by its high energy efficiency and wide output voltage range. The scheme can be suitably deployed in a multitude of novel edge-data processing systems.

The area of lightweight cryptography for constrained nodes has been quite well researched since the advent of RFID tags. However, the important issue of the <italic>integrated</italic> design of a secure, ultra-low power, small-footprint IoT <italic>transceiver</italic> has not received sufficient attention. The objective of this paper is to present such a transceiver and evaluate its data rate and power in the presence of the cryptographic overhead and compare its security with that of prior lightweight cryptographic algorithms. The proposed secure transceiver design is based on two main novel ingredients. The first is the Edge-Coded Signaling (ECS) protocol - a recently introduced technique for single-channel, high-data rate, low-power dynamic signaling that does not require any clock and data recovery. The second ingredient is a novel high-speed symmetric block cipher, HSA5/1, that is based on the well-known <inline-formula> <tex-math notation="LaTeX">$A5/1$ </tex-math></inline-formula> cipher and that generates a full keystream in one clock cycle. Both ingredients are combined to design a lightweight, high-speed, multilayer cipher with a tunable impact on ECS&#x2019;s power consumption, energy efficiency, and data rate. The multilayer cipher provides additional layers of packet security that make it difficult for an attacker to <italic>even</italic> receive a legitimate packet, let alone decrypt its data by attacking the HSA5/1 protocol itself. In addition, the multilayer encryption method may be easily configured to modulate the communication security overhead as a function of the number of clock cycles made available to the encryption/decryption stage. The secure ECS transceiver is prototyped and verified on both an embedded and an FPGA platform. It has also been synthesized for an ASIC implementation in <inline-formula> <tex-math notation="LaTeX">$65nm$ </tex-math></inline-formula> CMOS technology that is shown to preserve the low-power operation of ECS, consuming only <inline-formula> <tex-math notation="LaTeX">$27~\mu W$ </tex-math></inline-formula> of power at a clock frequency of <inline-formula> <tex-math notation="LaTeX">$25MHz$ </tex-math></inline-formula> while requiring only one clock cycle for executing 148-bit-key encryption/decryption unit.

The paper presents a novel transmitter architecture for short-range asynchronous wireless communication, applicable to simultaneous multi-user wireless acquisition of biological signals. The analog signal, provided from an analog biosensor, is transformed to time information using an Integral Pulse Frequency Modulator (IPFM) as a Time-Encoding Machine. The IPFM generates a time-encoded unipolar pulse train, maintaining the linear dependence of the output pulse distance on analog input voltage. The system enables continuous acquisition of the signals from multiple sensors in which each transmitter has unique feedback loop delay used for multi-user coding. IPFM pulses trigger the Impulse Radio Ultra-Wideband pulse generator directly, providing two ultra-wideband (UWB) pulses per each IPFM pulse. Due to the lack of internal clock signal and microprocessor-free multi-user coding, the circuitry satisfies the requirements of multi-user coding energy efficiency and size reduction, which are crucial demands in biomedical applications. The proposed Time-Encoded UWB (TE-UWB) transmitter is implemented in 0.18 [Formula: see text] CMOS technology. Measurement results of the IPFM transfer function for input voltage ranging from 0.15 to 1.5 V are presented, providing the dependence of the IPFM pulse time distance on analog input voltage and power consumption dependence on the input voltage level. For continuous monitoring operation, total power consumption of the transmitter circuitry for the maximum input voltage is 10.8 [Formula: see text], while for the lowest input voltage it increases to 40.48[Formula: see text]. The circuit occupies 0.14 [Formula: see text].

Energy efficiency has gained its significance when service providers' operational costs burden with the rapidly growing data traffic demand in cellular networks. In this paper, we propose an energy efficiency model for Poisson-Voronoi tessellation (PVT) cellular networks considering spatial distributions of traffic load and power consumption. The spatial distributions of traffic load and power consumption are derived for a typical PVT cell, and can be directly extended to the whole PVT cellular network based on the Palm theory. Furthermore, the energy efficiency of PVT cellular networks is evaluated by taking into account traffic load characteristics, wireless channel effects and interference. Both numerical and Monte Carlo simulations are conducted to evaluate the performance of the energy efficiency model in PVT cellular networks. These simulation results demonstrate that there exist maximal limits for energy efficiency in PVT cellular networks for given wireless channel conditions and user intensity in a cell.

This paper presents a fully digital quantization noise reduction algorithm (DQNRA) for $\mathrm {CT}\Sigma \Delta \mathrm {M}$ . The algorithm overcomes the signal leakage issues commonly found in cascade and MASH implementations. The proposed DQNRA is robust to PVT variations. The DQNRA performs a foreground measurement of the modulators noise transfer function. A $\Sigma \Delta \mathrm {M}$ using a 7 bit quantizer, from which the four most significant bits are used for the operation of the $\Sigma \Delta \mathrm {M}$ , proves the DQNRA concept. The remaining three least significant bits are used for the realization of the DQNRA for quantization noise improvement. A 7 bit quantizer with a three-step subranging architecture is implemented to reduce power and area consumption. A fourth-order continuous-time $\Sigma \Delta $ prototype was implemented in 130 nm CMOS technology. The modulator’s total power consumption is 20 mW, with only 6 mW used for the realization of the 7 bit quantizer operating at 500 MHz. For this prototype, the use of a DQNRA algorithm improved the modulator’s SNDR from 69 to 75 dB over a 15 MHz bandwidth, limited after calibration by thermal noise rather than quantization noise. The obtained FoM is 164 dB.

A fully integrated transmitter architecture operating in the charge-domain with incremental signaling is presented. The architecture provides improved out-of-band noise performance, thanks to an intrinsic low-pass noise filtering capability, reduced quantization noise scaled by capacitance ratios, and sinc 2 alias attenuation due to a quasi-linear reconstruction interpolation. With a respective unit and baseband capacitances of 2 fF and 45 pF, the architecture attains a potential 14 bit equivalent quantization noise with a 1024 unit capacitance array. Using four 10 bit charge-based DACs (QDACs) at 128 MS/s sampling rate, it achieves $-$ 155 dBc/Hz at 45 MHz offset from a 1 GHz modulated carrier. The incremental-charge-based operation also leads to an improved efficiency at back-off conditions. For an average output power of 1 dBm (20 MHz BW), total power consumption is 41.3 mW, of which only 0.5 mW corresponds to the system charge intake. The prototype is implemented using a 28 nm 0.9 V CMOS technology, with a core area of 0.25 mm 2 . With a reduced sampling frequency and number of bits, power and area consumption are among the best and will directly benefit from future technology scaling .