Communication-Aware Globally-Coordinated On-Chip Networks

Network on Chip (NoC) has been proposed as a new paradigm for designing System on Chip (SoC) which supports high degree of scalability and reusability. One of the most important issues in an NoC design is how to map an application on NoC-based architecture in order to satisfy the performance and cost requirements. In this paper a novel procedure is introduced to find an optimal application-specific NoC using Particle Swarm Optimization (PSO) and a linear function which considers communication cost, robustness index and contention factor. Communication cost is a common metric in evaluation of different mapping algorithms which have direct impact on power consumption and performance of the mapped NoC. Robustness index is used as a criterion for estimating fault-tolerant properties of NoCs and contention factor highly affects the latency, throughput and communication energy consumption. The experimental results on two real core graphs VOPD and MPEG-4 reveal the power of proposed procedure to explore design space and how effective designer can customize and prioritize the impact of metrics.

Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC with low hardware overhead, matching the application requirements are essential. In this work, we present a method for reducing the hardware complexity of the NoC by automatically configuring the architecture of the NoC switches to suit the application traffic characteristics. The crossbar matrix and the arbiters of each switch in the NoC design are customized to support the traffic flows utilizing that switch. This application- specific switch customization is integrated with an existing design flow, which automates NoC topology synthesis, mapping, RTL code and physical layout generation. Several experimental studies on NoC benchmark designs are carried out, which show that the proposed switch customization technique leads to large reduction in the NoC switch area (28% on average) and power consumption (21% on average). Moreover, the critical paths of the switches reduce significantly, thereby leading to a significant speed-up of the NoC design.

Two network-on-chip (NoC) designs are examined and compared in this paper. One design applies a bidirectional ring connection scheme, while the other design applies a code-division multiple-access (CDMA) connection scheme. Both of the designs apply globally asynchronous locally synchronous (GALS) scheme in order to deal with the issue of transferring data in a multiple-clock-domain environment of an on-chip system. The two NoC designs are compared with each other by their network structures, data transfer principles, network node structures, and their asynchronous designs. Both the synchronous and the asynchronous designs of the two on-chip networks are realized using a hardware-description language (HDL) in order to make the entire designs suit the commonly used synchronous design tools and flow. The performance estimation and comparison of the two NoC designs which are based on the HDL realizations are addressed. By comparing the two NoC designs, the advantages and disadvantages of applying direct connection and CDMA connection schemes in an on-chip communication network are discussed.

In this paper, we will study the on-chip network and memory hierarchy design of the Godson-T - a homogeneous many-core processor. Godson-T has 64 cores (with private L1 cache), and 16 global L2 cache banks. All these on-chip units are connected by a 2D 8 × 8 mesh network. Our study reveals that:(a) Global on-chip L2 cache can effectively alleviate the memory pressure caused by the data-thirsty on-chip computing engines. However, its potential is still limited by both the off-chip and the in-chip bandwidth, especially when increasing the number of active threads.(b) On-chip traffic congestion is largely caused by the intensive memory access requests issued from the on-chipcores. Therefore, the design of the on-chip network must consider the available performance of the datapath that connects the processor to the main memory. (c) In theory, different applications have different communication patterns (Berkeley's view). However, the application's runtime communication pattern is only determined by the design of the underlying memory hierarchy and on-chip interconnection. These conclusions are generally applicable to a wide variety of many-core processors with similar design.

The continuous improving of semiconductor technology integrates more processors into a single chip. While integrate multiple processors into a chip, the interconnection network of among the cores become a dominant performance bottleneck. Accordingly, this paper provides a new on-chip interconnection network, called Self Similar Cubic (SSC), for many-core architectures. By cooperating with proposed linking mechanism, routing algorithm, and switching architectures, SSC has better scalability, on-chip fabrication possibility, and high communication performance, than conventional on-chip networks, such as Mesh, and Hypercube. In this paper, the comparison of performance and area cost are proposed. The analysis results reveal that SSC can provide higher throughput and lower area cost than other on-chip networks. The performance per area cost of SSC is five times better than that of Mesh.

The density of integration in a single chip has progressed by use of the deep submicron of VLSI design rule. Systems on a chip (for short, SoCs), i.e., several functional cores being integrated in a single chip, have become the mainstream technology. On the other hand, A Network on a Chip (NoC), i.e., a communication-centric platform, offers an on-chip interconnection network. The NoC is one of the on-chip communication systems. The NoC is used in place of conventional shared bus systems. There are many NoC topologies for connecting cores to each other, such as Mesh, Ring, Spider on, and so on. To evaluate the NoC topologies, a simulation based approach was used for the modeling and analysis of the topologies. However, some properties of the topologies could affect the performance of the NoC systems. This paper describes about the performances of the topologies about the communication aspects by the simulation based approach.

Network-on-Chip (NoC) architectures have been proposed as a promising alternative to classic bus-based communication architectures. In NoC design, power efficiency is a crucial concern that runs through the whole synthesis process, such as topology generation, mapping, routing, et al. However, it is hard to converge at the final layout generation stage since different stages have different design objects. In this paper, we present an incremental power-aware layout optimization method based on a Mixed Integer Linear Programming (MILP) model at post-layout stage in NoC design. Experimental results show that our optimization flow can achieve 23.3% power reduction on wires with a reasonable runtime while both the area and chip performance would not compromise.

Multi-processor System-on-Chip (MPSoC) architectures in future will be imple- mented in less than 50 nm technology and include tens to hundreds of process- ing element blocks operating in the multi-GHz range. The on-chip interconnec- tion network will be a key factor in determining the performance and power consumption of these multi-core devices. Packet switched interconnection net- works or Network-on-Chip (NoC) has emerged as an attractive alternative to tra- ditional bus-based architectures for satisfying the communication requirements of these MPSoC architectures. The key challenge in NoC design is to produce a complex, high performance and low energy architecture under tight time to market requirements. The NoC architectures would support the communication demands of hundreds of cores under stringent performance constraints. In addi- tion to the complexity, the NoC designers would also have to contend with the physical challenges of design in nanoscale technologies. The NoC design prob- lem would entail a joint optimization of the system-level floorplan and power consumption of the network. All these factors coupled with the requirement for short turn around times raises the need for an intellectual property (IP) re-use methodology that is well supported with design and optimization techniques, and performance evaluation models. This chapter introduces the concept of NoC and presents the various elements of the IP-based system-level methodology required for its design.

The network-on-chip(NoC) is one of important aspects in digital circuit design, it attracted more and more attentions in electronic engineering. The NoC has been proposed as a promising solution to act as communication architecture because the number of cores in the systems-on-chip(SoC) is increased greatly. A lot of work needs to be carried out in the design of NoC, such as the determinations of the NoC communication backbone and communication protocols, the allocation of cores to various available nodes in NoC topology, that is the core mapping. The task of core mapping is to determine the topological placement of cores onto the nodes in NoC topology structure, and choose a path for each pair of IP cores. In this paper, the NoC structure with mesh topology is considered, a new approach is presented for the core mapping of network-on-chip by using Tabu search algorithm. The evolution operations in genetic algorithms are added to the Tabu search process to enhance the computation efficiency. The experimental results show that the time being needed to obtain the core mapping scheme by the approach proposed in this paper is lower than conventional genetic algorithm.KeywordsDigital circuitsnetwork-on-chipscore mappingTabu search algorithmgenetic algorithms

Network-on-chip (NOC) is emerging as a revolutionary methodology to integrate numerous intellectual property blocks in a single die. It is the packet switching-based communications backbone that interconnects the components on multicore system-on-chip (SoC). A major challenge that NOC design is expected to face is related to the intrinsic unreliability of the interconnect infrastructure under technology limitations. By incorporating error control coding schemes along the interconnects, NOC architectures are able to provide correct functionality in the presence of different sources of transient noise and yet have lower overall energy dissipation. In this paper, designs of novel joint crosstalk avoidance and triple-error-correction/quadruple-error-detection codes are proposed, and their performance is evaluated in different NOC fabrics. It is demonstrated that the proposed codes outperform other existing coding schemes in making NOC fabrics reliable and energy efficient, with lower latency.

Network on Chip (NoC) is an enabling methodology of integrating a very high number of intellectual property (IP) blocks in a single System on Chip (SoC). A major challenge that NoC design is expect...

Multiprocessor system-on-chips (MPSoCs) and chip multiprocessors (CMPs) are moving towards the integration of hundreds of heterogeneous cores on a single chip. Network-on-Chip (NoC) has been the superior interconnect fabric for MPSoCs and CMPs. Due to the rise of dark silicon with the end of Dennard Scaling, it becomes essential to design energy-efficient and high performance reconfigurable NoC between heterogeneous components based on the applications workloads (e.g., task communication demands). Because of the large and complex NoC design space in heterogeneous architectures (link bandwidth, big/little cores and routers, number of components, etc.), it becomes difficult to explore within a reasonable time for optimal trade-offs of energy-performance. Furthermore, reactive resource configuration of NoC is not effective in reducing power consumption. Therefore, we propose reinforcement learning (RL) technique to proactively configure the NoC link-bandwidths in heterogeneous architectures for energy-efficiency. NoC link-bandwidths are configured dynamically based on the learning of the system (e.g., link utilization, buffer utilization). RL agent automatically learns from past and current experiences and take the configuration decision intelligently on heterogeneous architectures to achieve its objective. Simulations under real-world benchmarks show that RL based technique reduces the energy-delay product by 30% and improves the throughput by 50% compared to non-machine learning based solutions.

On-chip network design has become an increasingly important component of computer architecture. the cell broadband engine's element interconnect bus, with its four data rings and common command bus for end-to-end transaction control, interconnects more nodes than most commercial on- chip networks. to help understand on-chip network design and performance issues in the context of a commercial multicore chip, this article evaluates the ElB network using conventional latency and throughput characterization methods.

Computer architecture is transiting from the multicore era into the heterogeneous era in which heterogeneous architectures use on-chip networks to access shared resources and how a network is configured will likely have a significant impact on overall performance and power consumption. Recently, heterogeneous network on chip (NoC) has been proposed not only to achieve performance comparable to that of the NoCs with buffered routers but also to reduce buffer cost and energy consumption. However, heterogeneous NoC design for heterogeneous GPU-CPU architectures has not been studied in depth. This paper first evaluates the performance and power consumption of a variety of static hot-potato based heterogeneous NoCs with different buffered and bufferless router placements, which is helpful to explore the design space for heterogeneous GPU-CPU interconnection. Then it proposes Unidirectional Flow Control (UFC), a simple credit-based flow control mechanism for heterogeneous NoC in GPU-CPU architectures to control network congestion. UFC can guarantee that there are always unoccupied entries in buffered routers to receive flits coming from adjacent bufferless routers. Our evaluations show that when compared to hot-potato routing, UFC improves performance by an average of 14.1% with energy increased by an average of 5.3% only.

Increasing the number of virtual channels can improve the throughput in an on-chip interconnection network. High throughput butterfly fat tree (HTBFT) architecture to achieve high performance networks on chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to butterfly fat tree switch.