Communication performance over a gigabit Ethernet network

This paper reports recent work on gigabit Ethernet interconnection communication traffic analysis. We proposed and demonstrated the system concept of gigabit Ethernet communication. 1.25Gbps, 10Gpbs and 40Gpbs gigabit Ethernet interconnection networks are considered for computer communications. Various switching structures, such as crossbar, double crossbar (Dcrossbar), Modified Dilated Benes (MDB), General MDB (GMDB), Benes, Dilated Benes (Dbenes), Tree architecture, Simplified tree (Stree), Extended baseline network (Ebaseline) are analyzed for searching the optimal performance of gigabit Ethernet communication. The numerical results for computation information transferring can be applied to search a best strategy for gigabit Ethernet communication networks interconnections.

Next generation experiments of high energy physics produce a lot of amount of data with high rate. That requires collecting data with higher rate than the present one. The traditional data acquisition (DAQ) system, however, doesn't work well for such high requirements. Many Studies, therefore, are being performed with switching network technologies, such as ATM, FiberChannel, FastEthernet, SCI, and so on. We have studied one of high speed switching networks, Gigabit Ethernet, for an application to an event builder. The system with global traffic control method is also useful for the event builder with Gigabit Ethernet technology.

Employing transport layer multi-railing in cluster networks

Compliance with the end-to-end latency of tasks and flows is a safety-relevant constraint in real-time systems. Especially when tasks and flows are interconnected by data dependencies in so-called Cause-Effect Chains, the adherence to end-to-end restrictions becomes even more complex. In our previous work, we proposed the incremental algorithm ITANS, which presents a solution for the joint scheduling of tasks and flows organized in Cause-Effect-Chains in communication networks applying the IEEE 802.1Qbv Time-Aware Shaper. In this work, we extend the approach to communication networks using the scheduling method Strict Priority (SP). The determination of the worst-case transmission time (WCTT) of flows is an essential part of ITANS. To derive the WCTT of flows in SP-based networks, we use the mathematical framework Network Calculus (NC) combining existing analyses to derive the least pessimistic delay guarantees for network flows. The evaluations show that the extension of ITANS can achieve a high success rate and a low runtime on average in systems with Gigabit Ethernet and communication networks that use SP.

FPGA(Field-programmable gate array) is programmable device, characterized by high speed and reconfiguration. We could test the circuit programmed by HDL (Hardware Description Language). By observing results of simulations through ModelSim, developers could fix logic errors. Also, they could analyze performance of circuits by the results. In the system, we build the Gigabit Ethernet development platform based on a FPGA. This paper presents the technique of FPGA and Gigabit Ethernet, as well as relevant techniques. On the basis of merits and drawbacks of different design proposals and real demands, we take the EP3C10E144C8N chip belonging to the series of Cyclone III produced by Altera corp. as main controller chip. By the use of an AX88180 MAC chip produced by ASIX Electronics Corporation and a RTL8211E physical chip by Realtek Semiconductor Corporation, we build the development platform. At the receiving end, we capture data frames from the network adapter by winpcap programming and throw video data in the buffer. Considering large amounts of data in the real-time transportation, we design fixed-length queue as the primary structures for buffer. Size of a buffer unit is 32KB, which means that 32 packets can fill the buffer. When the buffer is full, we put the buffer unit to the end of the queue. We get data from buffer and hand it over to application process to display and store video data. When packet loss is detected by the system, log file will record it and thus we can check how many packets lose. The simulations by Quartus II and practical application proves that the system is stable, featuring high speed and low cost. It can be used in various high speed real-time transmission with little modification.

The applications based on traditional digital cameras have been limited by distance, cost and networking. Gigabit Ethernet is a data transmission standard based on the IEEE 802.3 protocol, brings several benefits to image transmission. In this paper, we compare the main features of Gigabit Ethernet and traditional digital camera interfaces. And, we design a high speed image acquisition system which overcomes these application limitations by allowing cameras to send imaging data over Gigabit Ethernet. In this system, we design a highly efficient, bidirectional conversion device based on FPGA, converts imaging data from a camera to IP packets based on UDP protocol, and sends it to PCs over inexpensive Cat-5 copper LAN cable. At the PC, the Cat-5 cable plugs into a standard Gigabit Ethernet NIC(network interface card), eliminating the need for a frame grabber. An communications application software is used to acquire the network data, construct and display the image. A simple and efficient acknowledge and resend mechanism was used to guarantee packet delivery. The system architecture and the communication protocol are discussed in details, the experiment and results are presented in this paper.

With the advent of Gigabit Ethernet network technology, a new contender for the next-generation cluster interconnect is on the horizon. We benchmark Gigabit Ethernet and compare it to other cluster interconnects, namely Fast Ethernet, Myrinet and Scalable Coherent Interface. For a meaningful comparison, benchmark experiments are carried out at two levels: TCP/IP networking and MPI parallel programming. Using high-end PCs (Pentium III 450 MHz) and standard system software (Linux and MPICH), our results show that with Gigabit Ethernet, end-to-end throughputs of up to 44 MBytes per second can be achieved. A change from Fast Ethernet to Gigabit Ethernet resulted in performance gains of up to a factor of 5.05 for ftp, up to a factor of 3.10 for MPI point-to-point communication and up to a factor of 2.58 for some NAS parallel benchmarks, depending on communication granularity and message size. Further performance gains seem to require improved protocol processing and node hardware (memory bandwidth, file system, PCI bus).

This paper presents a performance study of a nonrigid registration algorithm for investigating lung disease on clusters. Our algorithm combines two conventional acceleration techniques in order to achieve fast registration: a data-parallel processing technique for accelerating the registration procedure; and a precomputation technique for reducing the computational complexity. We perform some experiments on three clusters with different CPU and network performance in order to make clear what kinds of acceleration techniques and computing environments provide higher performance. The results show that a cluster with Gigabit Ethernet (GbE) network is the most cost effective solution that reduces registration time from ten hours to ten minutes with a linear speedup.

: This report documents the installation, acceptance testing, vendor interactions, and final system acceptance for production usage of a dedicated high performance computing project investment that was installed at the U.S. Army Research Laboratory facilities on the Aberdeen Proving Ground in MD. The uniqueness of this system lies in the use of the low latency 10 GigE (gigabit Ethernet) network fabric, many-core AMD Opteron central processing units (CPUs), Nvidia Fermi graphics processing unties (GPUs), and a mixture of CPU-only and CPU/GPU nodes. The final accepted production system is stable and capable of nearly 1 PetaFLOPS (1012 floating-point operations per second) of single precision performance.

A half duplex repeater is the cheapest method for connecting multiple hosts to an IEEE 802.3 Ethernet LAN. However, if we increase the data rate from 10 Mb/s Ethernet to 100 Mb/s Fast Ethernet, shared access via CSMA/CD becomes less efficient because of the resulting increase in size of the collision fragments. For example, in a typical star wired single repeater network with a diameter of 200 meters, upgrading from 10BASE-T to 100BASE-T increases the round trip delay from about 100 bit times to almost 500 bit times. Moreover, a further upgrade to 1000 Mb/s Gigabit Ethernet would increase the round trip delay to about 4000 bit times. We introduce a simple change to the handling of incoming signals at the repeater ports known as collision truncation, and show that it reduces the average duration of a collision by more than 50% for networks with large round trip delays. For the standard BEB Ethernet protocol operating at moderate load, collision truncation reduces the mean end to end network delay by more than 25% for 100 Mb/s Fast Ethernet and by more than 50% for 1000 Mb/s Gigabit Ethernet. For BLAM, collision truncation increases the maximum throughput by more than 10%, and reduces the mean end to end delay substantially under high load. Collision truncation requires no changes to the host network adapters, and its use is completely transparent to the hosts. The only behavioral change that is visible to the attached hosts is the illusion that the network diameter appears to have been reduced. The relative cost of adding collision truncation to a repeater is very small compared to upgrading to a frame level device, such as a bridge.

The deployment of Gigabit Ethernet in corporate and ISP networks makes the transmission over WDM networks necessary to provide for the interconnection over metropolitan and wide area WDM networks. As the specifications of the optical signal between Gigabit Ethernet and the WDM-network mismatch, a transponder is needed. We propose an architecture for a Gigabit Ethernet over WDM transponder and report on a transponder prototype implementation. We further show how to use the transponder for Gigabit Ethernet networks over WDM rings.

Performance of 1 and 10 Gigabit Ethernet cards with server quality motherboards

Time synchronization is a critical feature for many scientific facilities and industrial infrastructures. The required performance is progressively increasing everyday, for instance, few tens of nanoseconds for Fifth Generation (5G) networks or sub-nanosecond accuracy on next family of particle accelerators and astrophysics telescopes. Due to this exigent accuracy, many applications require specific timing dedicated networks, increasing the system cost and complexity. Under this context, the new IEEE 1588-2019 High Accuracy (HA) default profile is intensively based on White Rabbit (WR) which can provide sub-nanosecond accurate synchronization for Ethernet networks. However, current WR solutions have not been designed to work properly with high data bandwidth delivery services even in 1 Gigabit Ethernet (GbE) links. On this contribution, the authors propose a new architecture design that enables WR and, consequently, the IEEE 1588-2019 HA profile to be deployed over 10 GbE links solving the already identified data bandwidth problem. Furthermore, this work addresses different experiments needed to characterize the system performance in terms of time synchronization and data transfer. As final result, this contribution presents for the first time in the literature a new WR system which allows high bandwidth data exchange in 10 GbE networks while providing sub-nanosecond accuracy synchronization. The proposed solution maintains the time synchronization performance of existing WR 1 GbE devices with significant advantages in terms of latency and data bandwidth, enabling its deployment in applications that integrate data and synchronization information in the same network.

This paper presents communication strategies for achieving efficient parallel and distributed Java applications on clusters with high-speed interconnects. Communication performance is critical for the overall cluster performance. Previous efforts at obtaining efficient Java communications have a limited applicability on high-speed interconnects as they are focused on high level APIs like RMI, ignoring the particularities of these systems and their native high performance communication protocols. By relying on a custom Java socket implementation higher degrees of performance can be achieved exploiting high-speed interconnect facilities. Several protocol definitions are presented, looking for obtaining high performance Java communications. Moreover, the quality of the protocol implementations and their design decisions has been thoroughly evaluated on a scalable coherent interface (SCI) and gigabit Ethernet (GbE) testbed cluster. The results of this analysis have demonstrated that these Java protocols obtain similar results to native communications

A high-speed interface has been designed for interconnection of the S/390® I/O subsystem to the IBM S/390 G5 processor. The self-timed interface (STI) provides high bandwidth, greater communication distances, and simpler timing within the S/390 servers than traditional interfaces. The STI communicates between the memory bus adapter and the expanded S/390 I/O subsystem, which now includes the new S/390 fiber channel offering (FICON™) and other network-based protocols such as ATM, Fast Ethernet, and Gigabit Ethernet. Also new for G5 is the use of STI for the integrated cluster bus (ICB), providing direct links among multiple G5 servers. The STI communicates over cables up to ten meters in length at a clock frequency of 167 MHz. Data is sent at twice the clock frequency (333 MB/s). The hardware implementation comprises specially designed logic macros, differential drivers and receivers, and the cables and connectors. The receive macro accommodates up to three bittimes of skew by retiming each data bit of the interface to the transmitted clock. This paper describes the STI logic, the characteristics of the link, and the transmission and reception of the data (and clock).