Communication studies of single-threaded and multithreaded distributed-memory machines

Simulating Spatially Explicit Problems on High Performance Architectures

The Fast Fourier Transform (FFT) is an efficient algorithm to calculate the Discrete Fourier Transform (DFT), which is often employed in Digital Signal Processing (DSP) and communication. In FFT, complex multiplication and addition units in the butterfly module consume most of the hardware resources. Compared to the addition operation, multiplication is more complicated. In this paper, the multiplier in the complex multiplication unit of the FFT is approximated. Four Radix-4 Booth multipliers with different approximation levels are proposed to reduce the hardware complexity. The pipeline FFT and the parallel FFT based on the proposed approximate multipliers are implemented and extensively evaluated. Compared with the state-of-the-art FFT designs, the LUTs amount is reduced up to 20.3% and 29.1% for pipeline and parallel FFTs, respectively. The power is reduced up to 69.9% for pipeline FFT, and the delay is reduced up to 45.7%. Moreover, the PSNR is reduced by less than 1dB in both pipeline FFT and parallel FFT. Proved by experiment results, the overall performance of the proposed designs is better than FFT designs using other approximate multipliers.

The difficulty of handling out-of-core data limits the potential of parallel machines and high-end supercomputers. Since writing an efficient out-of-core version of a program is a difficult task and since virtual memory systems do not perform well on scientific computations, we believe that there is a clear need for compiler-directed explicit I/O approach for out-of-core computations. In this paper, we present a compiler algorithm to optimize locality of disk accesses in out-of-core codes by choosing a good combination of file layouts on disks and loop transformations. The transformations change the access order of array data. Experimental results obtained on IBM SP-2 and Intel Paragon provide encouraging evidence that our approach is successful at optimizing programs which depend on disk-resident data in distributed-memory machines.

In this report we present parallel solvers for large linear systems arising from the finite-element discretization of the three-dimensional steady-state groundwater flow problem. Our solvers are based on multigrid and Krylov subspace methods. The parallel implementation is based on a domain decomposition strategy with explicit message passing using NX and MPI libraries. We have tested our parallel implementations on the Intel Paragon XP/S 150 supercomputer using up to 1024 parallel processors and on other parallel platforms such as SGI/Power Challenge Array, Cray/SGI Origin 2000, Convex Exemplar SPP-1200, and IBM SP using up to 64 processors. We show that multigrid can be a scalable algorithm on distributed memory machines. We demonstrate the effectiveness of parallel multigrid based solvers by solving problems requiring more than 70 million nodes in less than a minute. This is more than 25 times faster than the diagonal preconditioned conjugate gradient method which is one of the more popular methods for large sparse linear systems. Our results also show that multigrid as a stand alone solver works best for problems with smooth coefficients, but for rough coefficients it is best used as a preconditioner for a Krylov subspace method such as the conjugate gradient method. We show that even for extremely heterogeneous systems the multigrid pre-conditioned conjugate gradient method is at least 10 times faster than the diagonally preconditioned conjugate gradient method.

High Performance Fortran (HPF) is a data-parallel programming language that allows the programmer to specify the data decomposition onto the processors while the compiler takes care of the tedious tasks of communication generation and computation partitioning. Shifting some of the complex tasks from the user to the compiler should encourage programmers to write and port code to parallel machines especially if the compiler implements these tasks efficiently. In this paper, performance results and analysis of a subset of the SPEC92 is presented for the XL HPF compiler on IBM SP2 machines. In addition to obtaining good performance from the compiler, one of the the main concerns of HPF users is portability. Experimental results and analysis are presented in this paper to investigate performance portability (consistency) first across multiprocessor architectures and then across compilers. For performance portability across multiprocessor machines, the same XL HPF compiler used for the IBM SP2 distributed memory machine experiment is also used to compile and execute the same applications but on IBM SMP machines. The comparable speedup and behaviour obtained for both machines indicates that HPF compilers can be portable across different architectures. For performance portability across compilers, various HPF programming techniques and recommendations are introduced to increase the chances of obtaining performance consistency with different HPF compilers.

The analysis of rounding error in the one-dimensional fast Fourier transform (FFT) is extended to a class of generalized orthogonal transforms [1] with a common fast algorithm similar to the FFT algorithm. This class includes the BInary FOurier REpresentation (BIFORE) transform (BT) [2], the complex BT (CBT) [3], and the discrete Fourier transform (DFT). Expressions for the mean square error (MSE) in the two-dimensional BT, CBT, and FFT are derived. In the case of white input data, the mean square error-to-signal ratio is derived for the multidimensional generalized transforms. The error-to-signal ratio for the one-dimensional FFT derived by Kaneko and Liu is modified with improvement. Some comparisons among BIFORE, DFT, and Haar transforms are also included. The theoretical results for the two-dimensional FFT and BIFORE have been verified experimentally. The experimental results are in good agreement with the theoretical results for lower order sequences, but deviate as the order increases due to the actual manner of rounding in the digital computer.

The critical problem for multicasting is to find optimal multicast tree. Most popular multicast algorithms over WAN are usually based on either Dijkstra’s shortest path tree or Steiner tree, which assume that sender can send a message to the next destination node right away. This can lead to a non-optimal multicast tree as it ignores gap parameter in LogP model. From our preliminary study, we found that gap is very significant especially in WAN. In this paper, we take gap into consideration and propose a minimization technique, which apply gap parameters to Dijkstra’s shortest path algorithm to construct minimized shortest path trees. We compare the multicast latency of normal Dijkstra’s shortest path multicast tree and our minimized multicast tree with simulation. The results show that multicast tree based on our proposed algorithm can clearly out-perform the multicast tree based on Dijkstra’s algorithm. Our results further indicate that our proposed algorithm can perform very well when message size is large with lots of nodes.

The fast Fourier transform (FFT) is the cornerstone of many supercomputer applications and therefore needs careful performance tuning. Most often, however the real performance of the FFT implementations is far below the acceptable figures. In this paper we explore several strategies for performance optimisations of the FFT computation, such as enhancing instruction-level parallelism, loop merging, and reducing the memory loads and stores by using a special-purpose automatic loop unroller. Our approach is based on the principle of complete unrolling which we apply to modify the FT kernel of the NAS Parallel Benchmarks (NPB). In experiments on two different IBM SP2 platforms, our automatically generated unrolled FFT subroutine is shown to improve the performance between 40% and 53% in comparison with the original code. Further the execution time of the entire 3-D FFT mega-step of the benchmark is faster than when calls to a similar FFT subroutine from the vendor-optimised PESSL numerical library are used. Preliminary results suggest that the completely unrolled code also outperforms FFTW another high-performance FFT package. Finally, our approach for automatic generation of moderately optimised but specialised codes requires only a modest amount of programming effort.

The Fast Fourier Transform (FFT) is one of the most widely used computation kernels. Its performance is highly sensitive to the efficiency of its memory operations. In particular, when the FFT is applied on large problem sizes, the overall performance becomes almost totally memory bound. In those cases, the impact of the algorithm’s computational operations is demoted to minimal. This is probably why existing efforts on optimizing large size FFTs have been focused on optimizing the memory operation efficiency. The widely adopted approach in that regard is to adapt parameters external to the FFT algorithm, such as data layout, system software memory management, etc., to the needs of FFT’s memory operation pattern.In this paper, we look into the FFT internals for a way to mitigate FFT’s memory "boundness". The low efficiency of FFT’s memory operation, to a large degree, is incurred by the many strided data shuffles intrinsic to the algorithm, and made worse by the fact that many of those stride sizes are power-of-two. The strided data shuffling is already one of the hard workload patterns for memory system, and the power-of-two stride sizes make such a memory access pattern even more challenging. This power-of-two strided memory access pattern is the key problem that our paper addresses and represents our main contribution. Our key idea is a complete separation of the logic indexes and the physical indexes of the data internally accessed in FFT. By maintaining an efficient mapping between the logic indexes and the physical indexes through all passes, almost any stride sizes can be used and be further tuned. As the result, FFTs can be correctly carried out without the need for most of those worst power-of-two data shuffles. This greatly improves memory performance and in turn raises the overall performance. We compare our Shuffle-Light FFT (SLFFT) library with FFTW, a very widely used FFT library, and achieve the average speedup on 24.7% on problems sizes from 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> to 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">26</sup> , and the maximal speedup of 39.4%.

Sorting is an important component of many applications, and parallel sorting algorithms have been studied extensively in the last three decades. One of the earliest parallel sorting algorithms is bitonic sort, which is represented by a sorting network consisting of multiple butterfly stages. The paper studies bitonic sort on modern parallel machines which are relatively coarse grained and consist of only a modest number of nodes, thus requiring the mapping of many data elements to each processor. Under such a setting optimizing the bitonic sort algorithm becomes a question of mapping the data elements to processing nodes (data layout) such that communication is minimized. The authors developed a bitonic sort algorithm which minimizes the number of communication steps and optimizes the local computation. The resulting algorithm is faster than previous implementations, as experimental results collected on a 64 node Meiko CS-2 show.

Problem statement: In order to improve and implement Fast Fourier Transform (FFT), in general, an efficient parallel form in digital signal processor is necessary. The butterfly structure is an important role in FFT, because its symmetry form is suitable for hardware implementation. Although it can perform a symmetric structure, the performance will be reduced under the data-dependent flow characteristic. Even though recent research which calls as Novel Memory Reference Reduction Methods (NMRRM) for FFT focus on reduce memory reference in twiddle factor, the data-dependent property still exists. Approach:In this study, we propose an approach for FFT implementation on DSP from analog device company (ADI) which is based on data-independent property and still hold the property of low-memory reference. We have applied the proposed method of radix-2 FFT algorithm in low-memory reference on ADI BlackFin561 DSP. Results: Experimental results show the method can reduce 44.36% clock cycles comparing with the NMRRM FFT implementation and keep the low-memory reference property. Conclusions/Recommendations: From our algorithm, the results can be accepted and realized for DSP-based embedded system. In further, we will try to implement on different DSP-based system in order to improve the algorithm values.

Fast Fourier Transform (FFT) is the most basic and essential part of Software Defined Radio (SDR). Therefore, designing regular, reconfigurable, modular and low hardware complexity FFT computation block is very important. A single FFT block should be configurable for varying length FFT computation and also for computation of different transforms like DCT, DST etc. In this paper, the authors analyze implementation complexity and Noise to Signal Ratio (NSR) of Bruunpsilas FFT w.r.t. classical FFT for SDR. It is shown that, Bruunpsilas algorithm for FFT computation is ideally suited for SDR and should be used in preference over any classical FFT architecture for most practical cases.

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

In this paper, a new design method for small point fast Fourier transform (FFT) processor is proposed in order to satisfy the increased demands for low resource and power consumption in addition to high real-time performance in communication and control systems. Using 64 point FFT with radix-2, decimation in time (DIT) algorithm as the design objective, only an adder block and a multiplier block with pipeline structure and floating point arithmetic are adopted applying this design method. According to different classifications of twiddle factor, corresponding butterfly operations can be implemented to save the total calculation time to only 1100 clock cycles for 64 point FFT. In addition, multiple FFT processor blocks can be integrated for parallel computing to achieve higher data throughput rate. Compared with some other designs of 64 point FFT, the final results show that the proposed design has better real-time performance and lower system level complexity with the same amount of resources.

FFT(Fast Fourier Transform) 알고리즘에는 DIT(Decimation-In-Time)와 DIF(Decimation-In-Frequency)가 있다. DIF 알고리즘은 Radix-2/4/8 등의 다양한 종류와 그 구현 방법이 개발되어 사용되고 잇으나, DIT 알고리즘은 순차적인 출력을 낼 수 있는 장점이 있음에도 불구하고 다양한 알고리즘이 연구되지 못하였다. 이 논문에서는 새로운 DIT Radix-4 FFT의 나비연산기(butterfly) 구조를 제안하고 검증하였다. 제안 구조를 사용하여 64-point FFT 구조를 설계하고 Verilog로 코딩하여 구현함으로써 제안 구조의 효용성을 입증하였다. 48개의 곱셈기를 사용하여 합성하였으며 678만 게이트 수를 나타내었다. 따라서 제안된 DIT Radix-4 FFT 구조는 순차적인 FFT 출력을 필요로 하는 OFDM 통신용 SoC(System on a Chip)에 사용될 수 있을 것이다. Two basic FFT(Fast Fourier Transform) algorithms are the DIT(Decimation-In-Time) and the DIF (Decimation-In-Frequency). In spite of the advantage of the DIT algorithm is to generate a sequential output, various structures have not been made. In this paper, a new DIT Radix-4 FFT butterfly structure are proposed and implemented using Verilog coding. Through synthesis, it is shown that the 64-point FFT is implemented by 6.78 million gates. Since the proposed FFT structure has the advantage of a sequential output, it can be used in OFDM communication SoC(System on a Chip) which need a high speed FFT output.