Compact DSOP and Partial DSOP Forms

A family of subsets of an n-element set is k-intersecting if the intersection of every k subsets in the family is nonempty. A family is maximalk-intersecting if no subset can be added to the family without violating the k-intersection property. There is a one-to-one correspondence between the families of subsets and Boolean functions defined as follows: To each family of subsets, assign the Boolean function whose unit tuples are the characteristic vectors of the subsets.We show that a family of subsets is maximal 2-intersecting if and only if the corresponding Boolean function is monotone and selfdual. Asymptotics for the number of such families is obtained. Some properties of Boolean functions corresponding to k-intersecting families are established fork > 2.

Boolean functions are widely used because they can be used to precisely describe logical circuits. Properties of Boolean functions with respect to their applications to cryptography have been studied, but relationship between Boolean functions are rarely studied. This paper studies the independence of Boolean functions, gives necessary and sufficient conditions for judging whether two given Boolean functions are independent. Some enumeration formulae are given.

A function is odd-cycle-free if there are no with k an odd integer such that f(x1) = … = f(xk) = 1 and x1 + … + xk = 0. We show that one can distinguish odd-cycle-free functions from those ∊-far from being odd-cycle-free by making poly(1/∊) queries to an evaluation oracle. We give two proofs of this result, each shedding light on a different connection between testability of properties of Boolean functions and of dense graphs. The first problem we study is directly reducing testing linear-invariant properties of Boolean functions to testing associated graph properties. We show a black-box reduction from testing odd-cycle-freeness to testing bipartiteness of graphs. Such reductions have been shown previously (Král-Serra-Vena, Israel J. Math 2011; Shapira, STOC 2009) for monotone linear-invariant properties defined by forbidding solutions to a finite number of equations. But for odd-cycle-freeness whose description involves an infinite number of forbidden equations, a reduction to graph property testing was not previously known. If one could show such a reduction more generally for any linear-invariant property closed under restrictions to subspaces, then it would likely lead to a characterization of the one-sided testable linear-invariant properties, an open problem raised by Sudan. The second issue we study is whether there is an efficient canonical tester for linear-invariant properties of Boolean functions. A canonical tester for linear-invariant properties operates by picking a random linear subspace and then checking if the restriction of the input function to the subspace satisfies a fixed property or not. The question is whether for every linear-invariant property, there is a canonical tester for which there is only a polynomial blowup from the optimal query complexity. We answer the question affirmatively for odd-cycle-freeness. The general question still remains open.

A function f: Fn2 → {0, 1} is odd-cycle-free if there are no x1,..., xk e Fn2 with k an odd integer such that f(x1) =... = f(xk) = 1 and x1 +... + xk = 0. We show that one can distinguish odd-cycle-free functions from those e-far from being odd-cycle-free by making poly(1/e) queries to an evaluation oracle. We give two proofs of this result, each shedding light on a different connection between testability of properties of Boolean functions and of dense graphs.The first problem we study is directly reducing testing linear-invariant properties of Boolean functions to testing associated graph properties. We show a black-box reduction from testing odd-cycle-freeness to testing bipartiteness of graphs. Such reductions have been shown previously (Kral-Serra-Vena, Israel J. Math 2011; Shapira, STOC 2009) for monotone linear-invariant properties defined by forbidding solutions to a finite number of equations. But for odd-cycle-freeness whose description involves an infinite number of forbidden equations, a reduction to graph property testing was not previously known. If one could show such a reduction more generally for any linear-invariant property closed under restrictions to subspaces, then it would likely lead to a characterization of the one-sided testable linear-invariant properties, an open problem raised by Sudan.The second issue we study is whether there is an efficient canonical tester for linear-invariant properties of Boolean functions. A canonical tester for linear-invariant properties operates by picking a random linear subspace and then checking if the restriction of the input function to the subspace satisfies a fixed property or not. The question is whether for every linear-invariant property, there is a canonical tester for which there is only a polynomial blowup from the optimal query complexity. We answer the question affirmatively for odd-cycle-freeness. The general question still remains open.

In symmetric cryptology the resistance to attacks depends critically on the nonlinearity properties of the Boolean functions describing cipher components like Substitution boxes (S‐boxes). Some of the most effective methods known to generate functions that satisfy multiple criteria are based on evolutionary heuristics. In this paper, we improve on these algorithms by employing an adaptive strategy. Additionally, using recent improvements in the understanding of these combinatorial structures, we discover essential properties of the graph formed by affine equivalence classes of Boolean functions, which offers several advantages as a conceptual model for multiobjective seeking evolutionary heuristics. Finally, we propose the first major global cooperative effort to discover new bounds for cryptographic properties of Boolean functions.

In the study of property testing, a particularly important role has been played by linear invariant properties, i.e., properties of Boolean functions on the hypercube which are closed under linear transformations of the domain. Examples of such properties include linearity, Reed‐Muller codes, and Fourier sparsity. In this work, we describe a framework that can lead to a unified analysis of the testability of all linear‐invariant properties, drawing on techniques from additive combinatorics and from graph theory.Our main contributions here are the following: We introduce a simple combinatorial condition, which we call subspace‐heredity, and conjecture that any property of Boolean functions satisfying it can be efficiently tested. Verifying this conjecture will unify many individual results in this area. We show that if our conjecture holds, then one can obtain a simple combinatorial characterization of properties of Boolean functions that can be efficiently tested with one‐sided error, thus addressing a challenge posed by Sudan recently. We introduce a new technique for proving the testability of Boolean functions. The main tool we develop is an extension of Green's arithmetic regularity lemma. Using it, we verify a special case of the conjecture. Our approach here is motivated by techniques that proved to be very successful previously in studying the testability of graph properties.© 2013 Wiley Periodicals, Inc. Random Struct. Alg., 46, 232–260, 2015

In this paper, we show that checking some properties of Boolean functions which are given by the lists of monomials in their polynomial representations can be implemented in polynomial time. Multi-linear polynomials over GF(2) are often a convenient way to represent Boolean functions. There is a single polynomial for each Boolean function, and the length of the polynomial (i.e. the number of its monomials) which represents a function of n variables can be far less than 2n. Therefore, in some cases, polynomials are a compressed description of Boolean functions. Besides, polynomial representations of Boolean functions have applications in circuit lower bounds, computational learning, error-correcting codes, cryptography. We construct polynomial-time algorithms for checking some properties of Boolean functions which are given by the lists of monomials in their polynomial representations. The considered properties are self-anti-duality (evenness), self-duality, periodicity, 1-invariance (Mobius transform invariance, coincidence). Note that checking each of these properties directly by definition gives, in the general case, only exponential-time algorithms. The approach to construct our algorithms is the following. Firstly, we prove that if a Boolean function has a certain property then its polynomial has a special structure. And secondly, we check the property by its characterization, cutting negative cases by proven facts. More precisely, we analyze an exponential time algorithm and prove that if the number of steps of the algorithm exceeds a bound, which is polynomial in the input size, and may be computed in advance, then the input will be necessarily rejected.

Algebraic immunity is an important cryptographic property for Boolean functions against algebraic attacks. Constructions of Boolean functions with the maximum algebraic immunity (MAI Boolean functions) by using univariate polynomial representation of Boolean functions over finite fields have received more and more attention. In this paper, how to obtain more MAI Boolean functions from a known MAI Boolean function under univariate polynomial representation is further investigated. The sufficient condition of Boolean functions having the maximum algebraic immunity obtained by changing a known MAI Boolean function under univariate polynomial representation is given. With this condition, more balanced MAI Boolean functions under univariate polynomial representation can be obtained. The algebraic degree and the nonlinearity of these Boolean functions are analyzed.

Today, the most common abstraction level for manual design capture is at the so called register transfer level. At this level, all synchronous registers, latches and the combinational logic between the sequential elements are described in a hardware description language such as Verilog or VHDL. The description is then transformed into logic gate implementations based on a technology specific cell library, a procedure known as logic synthesis. This allows a designer to handle more complex design because detailed manual analysis need not be made at the logic gate level that is more tedious and error prone. Register transfer level is certainly not the only starting point for automated hardware synthesis. The analysis and synthesis of digital circuits are still being pushed toward even higher level of abstraction for manual manipulation. For example, macro block level specification and synthesis has been practiced in some design areas. The register transfer and macro block level design methodologies are part of the architecture and system level techniques to be discussed in this chapter.

Traditionally, the problems of binding and placement in the synthesis of digital circuits have been formulated and solved separately. However, placement and binding strongly interact and design decisions taken during these phases determine the interconnect structure. As feature sizes continue to decrease, the delay caused by signal propagation through interconnect more and more dominate the overall system performance. Hence, optimizing interconnect becomes increasingly important. In this paper, we propose for the first time an analytical approach to capture the placement and binding problems in a single, unified Mixed Integer Linear Programming (MILP) model which also allows minimizing the overall interconnect structure. Such a model can serve as a starting point for deriving efficient heuristics in that it captures all information required for a comprehensive analysis of the problem. The target architecture is a linear bit-slice datapath, however, the model can be easily extended to handle two-dimensional datapath models.

Variability in circuit delay is a significant challenge in the design and synthesis of digital circuits. While the challenge is being addressed at various levels of the design hierarchy, we argue that modern register-transfer level (RTL) synthesis tools can be enhanced to deal with this problem in an alternate, yet effective, manner. Our solution involves the design of variability- tolerant, correct circuits assuming common-case, rather than worst-case, values for critical path delays. We propose a methodology to design variability-tolerant circuits that can, at runtime, detect and efficiently recover from delay errors, which would be inevitably introduced due to the use of common-case delay values. Variability-agnostic designs are automatically transformed into variability-tolerant circuits by the introduction of shadow logic to detect and recover from runtime errors, while exploiting data speculation to derive performance benefits. For various benchmark circuits, we show that the area overhead imposed by our scheme is only 11.4% on an average, while achieving upto 16.3% performance speedup over margined designs.

We study properties of the parameter of a Boolean function known as the affinity level, which characterises the efficiency of the linearisation method of solving systems of Boolean equations, and relations between this parameter and parameters characterising other properties of Boolean functions.

Boolean functions are used as nonlinear filter functions and combiner functions in several stream ciphers. The security of these stream ciphers largely depends upon cryptographic properties of Boolean functions. Finding a balanced Boolean function with optimal cryptographic properties is an open research problem in the cryptographic community. Since the number of n-variable Boolean functions is $$2^{2^n}$$ , it is not computationally feasible to search the entire space of such functions for cryptographically significant functions when $$n \ge 6$$ . In general, the construction of Boolean functions with optimal or near optimal cryptographically significant properties is formulated as combinatorial optimization problems. In this paper, we apply the Genetic algorithm with the integration of a local search procedure called hybrid GA (HGA) searching for the Boolean functions with high nonlinearity and low autocorrelation. The performance of the Genetic algorithm depends upon the tuning parameters such as crossover mechanism, mutation probability, selection criteria, and the choice of fitness/cost function. To achieve an optimal trade-off among two cryptographic properties, the choice of the cost function plays an important role for finding an optimal solution. So our main focus is to construct balanced Boolean functions using HGA with a new cost function and compare it with existing cost functions. Our experimental results shows that the HGA is more efficient than GA and the new cost function is more efficient than existing cost functions for reaching the optimal solutions.

Algebraic thickness is an important property of Boolean functions. In this paper we give the relationship between algebraic thickness of Boolean functions with disjoint variables and their algebraic thickness, and derive some algebraic thicknesses of special Boolean functions. Furthermore, we prove the restrictive relationship of algebraic thickness between Boolean function and complement Boolean function, by this result the upper bounds on algebraic thickness of Boolean functions with small hamming weights and their complement Boolean functions are given. Finally, we summarize some lower or upper bounds on algebraic thickness of common Boolean functions.

In design systems for digital VLSI (very large integrated circuits), the BDD is used for VLSI verification, as well as for technologically independent optimization, performed as the first stage in the synthesis of logic circuits in various technological bases. BDD is an acyclic graph defining a Boolean function or a system of Boolean functions. Each vertex of this graph corresponds to the complete or reduced Shannon expansion formula. Having constructed BDD representation for systems of Boolean functions, it is possible to perform additional logical optimization based on the proposed method of searching for algebraic representations of cofactors (subfunctions) of the same BDD level in the form of a disjunction or conjunction of other cofactors of this BDD level. The method allows to reduce the number of literals by replacing the Shannon expansion formulas with simpler formulas that are disjunctions or conjunctions of cofactors, and to reduce the number of literals in specifying a system of Boolean functions. The number of literals in algebraic multilevel representations of systems of fully defined Boolean functions is the main optimization criterion in the synthesis of combinational circuits from library logic gates.