Comparative analysis based on the switching frequency of modulation techniques for MMC applications

THIS dissertation addresses the technical challenges associated with the operation and control of high-power modular multilevel converters. To improve the performance of modular multilevel converter (MMC), a generalized three-phase mathematical model with common-mode voltage (CMV) is proposed. By using the proposed mathematical model, the magnitude of circulating currents, capacitors voltage ripple, and the ripple in DC-link current during balanced and unbalanced operating conditions can be minimized. The modulation scheme and switching frequency are directly affected the output power quality and the performance of the converter and control method. In this dissertation, a novel sampled average and space vector modulation scheme is proposed. These modulation schemes are suitable to control the MMC with any number of submodules (without modifications), operates at low switching frequency, minimizes the ripple in output current and voltage harmonic distortion, and reduces the output filter size. For reliable operation of MMC, the voltage balancing among submodules is mandatory. This dissertation proposes a generalized single-stage balancing approach with reduced current sensors to control the MMC. The proposed balancing approach is suitable to implement with both phase-shifted and level-shifted pulse width modulation schemes. With the proposed approach, it is also possible to control the MMC with half-bridge and three level flying capacitor submodules. Also, an improved balancing approach often referred as the dual-stage balancing approach is proposed to minimize the voltage harmonic distortion and device power losses. This dissertation also proposes a direct model predictive control (D-MPC) approach to minimize the ripple in submodule capacitors voltage. To implement D-MPC approach, a discrete-time model of MMC with CMV is proposed. With the use of proposed model, the D-MPC approach does not require a cost function to minimize the circulating currents. The computational complexity is one of the major issues in the implementation of D-MPC approach for MMC. In this dissertation, a novel reduced computational MPC approaches named as dual-stage D-MPC and indirect model predictive control (I-MPC) approach are proposed. These approaches significantly minimize the computational complexity and, improve the voltage and current waveform quality while operating at the low switching frequency. Finally, the simulation and experimental studies are presented to validate the dynamic and steady-state performance of proposed methodologies. Index Terms • Modular Multilevel Converters. • Capacitors Voltage Balancing. • Pulse Width Modulation Schemes. • Circulating Currents. • Capacitors Voltage Ripple • Direct Model Predictive Control. • Dual-Stage Direct Model Predictive Control. • Indirect Model Predictive Control. • Total Harmonic Distortion.

Modulation strategy plays an important role in the good performance of modular multilevel converter (MMC). Since MMC has a special structure as well as a large number of submodules (SMs), it is almost impossible to apply the conventional multilevel space vector modulation (SVM) algorithm in it. In this study, a simplified SVM implementation method is proposed by grouping SMs. With the presented method, the high‐level SVM process for MMC can be easily done by implementing multiple two‐level or three‐level SVM algorithm, while the complicated offline or online efforts/tasks about mapping switching states or sequences in the conventional multilevel SVM are not necessary any more. In order to improve the harmonic characteristics, the sampling time of different subunits (SUs), each of which is formed by grouping a few SMs, is staggered evenly, which helps to achieve a higher equivalent switching frequency and less low‐order harmonics. Further, the capacitor voltage balance of SMs is improved by rotation strategies between SUs or inside each SU even without any capacitor voltage detecting or sorting. Since the presented method is independent of the number of SMs, it can be very easily expanded into a high‐level MMC. These propositions are verified by experiment.

Submodule (SM) failure is one of the key factors leading to instability in modular multilevel converter (MMC) systems. To address this challenge and enhance system reliability, redundant configurations have become the core solution. However, existing redundancy strategies cannot simultaneously balance the transient repair speed and steady‐state output accuracy. Hence, a novel fusion redundant control scheme that combines cold‐standby and hot‐standby redundancy strategies is proposed to overcome the challenge of optimizing both transient repair speed and steady‐state output accuracy. First, an MMC structure is proposed, which is equipped with both cold‐standby SMs and hot‐standby SMs and realizes the sharing of cold standby SMs. Then, the casting and switching strategies of the SMs are designed based on this structure. Finally, a bridge arm reference voltage update module is designed to avoid the voltage offset caused by the coordination of the cold‐standby module and the hot standby module. Simulation and experimental results confirm that the proposed method effectively addresses both transient and steady‐state performance issues, facilitates rapid repairs, and ensures precise and reliable operation of the MMC system after a fault event.

To implement the STATCOMs for transmission and distribution applications, high power converters are needed. A multilevel converter is a logical choice for such applications as it can meet the imposed line side current and voltage harmonic distortion standards without extending its device ratings. Several types of monolithic multilevel converters have been proposed based on different structures of a DC link voltage (or current) to generate staircase output voltage (or current) levels. The multilevel current source converters (CSC) are also a potential configuration for STATCOM. Multilevel CSCs using fully controllable switches have the advantages of low output harmonics and controllable active and reactive power. During the last decade, modular multilevel converters have shown a breakthrough and have made their way to commercial high power applications. Modularity, in general, refers to a technique to develop comparably large systems by combining smaller subsystems. For power converter topologies, this means, a cascaded connection of converter cells seems to be an interesting solution to reach high voltage and high quality waveforms with a minimum complexity. This chapter provides an overview on monolithic and modular multilevel converter topologies, targeting high-power applications and in particular STATCOM. Modular multilevel converters can be built either straightforward by applying the modular building block cells or by a combination of cells with monolithic multilevel topologies. The monolithic and modular CSCs can also be realized by employing the duality concept on each corresponding Voltage Source Converter (VSC). This chapter summarizes the most recent developments made for multilevel converter topologies, by covering new promising topologies and operational issues. In addition, emerging trends, challenges, and possible future directions of the multilevel converter technologies are outlined.

Modular Multilevel Converter (MMC) has been widely used in medium/high voltage direct current transmission, motor drive, and renewable energy power generation, etc. The reliability requirements of MMC system which is composed of sub-modules(SM) as building blocks, are getting crucial. However, the testing for reliability of SMs in a full MMC system is time consuming and costly. In this paper, a mission profile emulator for SMs in MMC system is therefore focused, by using this mission profile emulator, the SMs can be tested individually without building a full MMC system. Simulation results show that the mission profiles of the SM under test is well agrees with the SM in a complete MMC system.

The modular multilevel converter (MMC) is emerged as the most favourable multilevel converter topology for medium to high-voltage applications. Reliability is one of the major concerns in an MMC due to high fragile component count. Due to low-cost and high energy density, electrolytic capacitors (ECs) are usually preferred as floating capacitors in the MMC. However, the ECs are gradually degraded over the time due to inherent chemical processes, which results in a decrease in capacitance value. This results in an increase in voltage ripple across the SM capacitors and would distort the output waveforms. Moreover, the prolonged use of these aged capacitors could disrupt the MMC operation. Therefore, monitoring and failure detection of submodule (SM) capacitors in an MMC are pivotal to enhance the reliability. This paper presents an SM capacitance estimation strategy for an MMC using nearest level modulation (NLM). A modified voltage balancing control structure with NLM is presented to reduce the unbalance in the capacitor voltages. The proposed approach uses available hardware for converter control with easy implementation in the same controller. Extensive studies are conducted on a three-phase MMC in PLECS simulation platform. Furthermore, experimental results are presented to substantiate the effectiveness of the proposed approach.

This paper presents a new converter topology for voltage source converter based high voltage dc application, named modular embedded multilevel converter (MEMC). MEMC is based on a three level structure and consists of series-connected IGBT bridge stacks, like the popular modular multilevel converter (MMC) and series-connected thyristor stacks. The IGBT bridge stacks are leveraged to generate the output the voltage waveforms and to commute the thyristors. The basic operation principle and the methods to commutate the thyristors are explained in detail. Due to the three level structure, the total number of IGBT stacks are reduced by half compared with MMC, leading to much lower energy storage, weight, volume and system complexity. Also by replacing part of the IGBT stack in MMC with thyristor stack, both of the system conduction loss and switching loss can be further reduced. The simulation results proved the analysis and verified the feasibility and benefits of the proposed converter topology.

The modular multilevel converter (MMC) is the state‐of‐the‐art for multilevel converter topologies. This study presents the operation of the MMC using the multilevel selective harmonic elimination pulse‐width modulation (MSHE‐PWM) technique. MSHE‐PWM offers tight control of the low‐order harmonics and the lowest switching frequency for the power semiconductors among all modulation techniques. A comprehensive analysis of the modulation methods for the MMC leads to two different modulation patterns for MSHE‐PWM. A method for selecting the number of sub‐modules in the phase‐legs of the converter is also proposed in this study. Simulation results for both patterns are provided and verified through matching experimental results from a single phase 11‐level laboratory prototype.

The digital control system of modular multilevel converters (MMCs) normally synchronizes with the switching actions. The switching frequency of an MMC is generally selected as low as possible from an efficiency point of view, which leads to an unavoidable and relatively long time delay in the control system. Such a time delay might deteriorate the MMC performance and even reduce the stability margin by introducing infinite uncertain eigenvalues into the system state functions. Without a proper time-delay model and quantitative system stability analyses, MMCs might suffer from uncertainties and unstable risks during their operations, especially when the switching frequency is low. This paper derives an MMC model considering the time delay in the digital control system. A Pade-based stability analysis method is then proposed, which consists of three steps: information integration and critical eigenvalue extraction, and trajectory visualization and critical angle (CA) calculation, and quantitative assessment and extreme value determination. By the proposed model and method, the critical eigenvalue can be effectively extracted. With the Hopf bifurcation, the time delay in the digital control system induces a pair critical conjugate eigenvalues into MMC systems, which is detected as an instability cause. The CA and the critical impact are defined to quantitatively assess the stability, while selecting the controller parameters and minimum switching frequency. The proposed method for the MMC stability assessment is experimentally verified.

Fractional frequency transmission system (FFTS) is a promising solution to offshore wind power integration. The back-to-back modular multilevel converter (MMC) and modular multilevel matrix converter (M3C) are universally regarded as two promising ac/ac converter candidates of the next generation. This paper performs a detailed comparison between back-to-back MMC and M3C with special emphasis on their total capacitor and semiconductor ratings. The arm current and capacitor ripples are first analyzed, then comparison results of a 220 kV, 500 MW case is given. In terms of peak-current-based and RMS-current-based total semiconductor ratings the M3C is 42.56 % and 22.97 % larger respectively, while its total capacitor rating is merely 33.15% of the back-to-back MMC. The better candidate can be determined according to the quantitative comparison results and the latest prices of semiconductors and capacitors.

Summary form only given. The modular multilevel converter (MMC) is a potential candidate for medium/high-power applications, specifically for high-voltage direct current (HVDC) transmission systems. One of the technical challenges associated with the control of an MMC is to carry out the submodule (SM) capacitor voltages balancing task without imposing any unnecessary switching transition among the SMs. This paper develops a general framework for the capacitor voltage balancing of an MMC. Based on the developed framework and with the objective of reducing the unnecessary switching transitions among the SMs, three capacitor voltage-balancing strategies are proposed and investigated: 1) a slow-rate balancing strategy based on the conventional sorting method; 2) a hybrid balancing strategy which combines a predictive method with the conventional sorting method; and 3) a fundamental-frequency balancing strategy. Performance of the proposed strategies for a point-to-point 21-level MMC-based HVDC system is evaluated based on time-domain simulation studies in the PSCAD/EMTDC software environment. The reported study results demonstrate the capability and tradeoffs of the proposed strategies to reduce the number of switching transitions and, consequently, the MMC losses, under various conditions.

The modular multilevel converter (MMC) is one of the most promising topologies for high- and medium-voltage applications. However, the conventional MMC relies on large arm inductance and complicated feedback control to maintain submodule (SM) capacitor voltages balanced, which requires a large number of voltage sensors and complicated arm current control loops. In contrast to the conventional perspective, the MMC can be regarded as a derivative from the general multilevel topology based on switched-capacitor (SC) structure. The SC structure endows excellent properties to the MMC, such as minimum or no arm inductor and automatic SM capacitor voltage balancing capability. This MMC with minimum or no arm inductor is named as SC-MMC. Since the arm inductances are very small, the SM capacitor voltages can be balanced automatically. Small stray/parasitic inductance is enough to limit inrush current during SM's switching instants to the rated current level. To unleash the automatic SM capacitor voltage balancing capability of the SC-MMC, a Y-matrix modulation (YMM) has been proposed, which does not require closed loop control or any sensor, has no limitations on the number of SMs, and works for both half-bridge and full-bridge SMs. An unresolved issue of the emerging YMM is that, in the published literature, the existence of the Y matrix with full rank has not been proved theoretically beyond the observation for the SC-MMC when the number of SMs is large. In this paper, an analytical proof of the existence of the full rank Y matrix is provided, which implies the automatic voltage balance of SMs for the MMC with arbitrary number of SMs in each arm. Simulation results using the YMM on a 21-level SC-MMC with minimum arm inductance are provided to verify the voltage balance theory/observation of the SC-MMC using the YMM.

The Modular Multilevel Converter (MMC) topology is getting popularized for the medium to high voltage applications after its inception. This paper presents a modified topology of the conventional MMC, named as Hybrid MMC (HMMC). This topology has reduced number of switch counts than the conventional MMC. Therefore, it is more efficient and has less complex circuitry than other existing multi-level topologies. In this paper a modified phase-shifted carrier pulse width modulation scheme (PS-PWM) is used for the switching of HMMC. The three-phase circuit is simulated in the Matlab/Simulink for different load conditions and the results are provided to validate the concepts behind the topology.

The thermal management plays an important role in improving the reliability and lifetime of high power converters, especially for the high voltage direct current (HVdc) transmission system. In the voltage source converter based HVdc systems (VSC-HVdc), the hybrid modular multilevel converters (MMCs) are taken as the excellent candidates due to their dc short-circuit fault ride-through ability and less submodule (SM) devices. Furthermore, the voltage modulation index of hybrid MMCs can be promoted to achieve higher power rating and efficiency. However, in this article, it is revealed that thermal stress distribution inside the SMs becomes more unbalanced under a high voltage modulation index, which would lead to serious thermal fatigue. To overcome this problem, the active bypass with thyristor for half-bridge submodules (HBSMs) and symmetrical modulation for full-bridge submodules (FBSMs) based active thermal control strategies are employed. With the presented thermal control strategies, the junction temperature of the most stressed devices in both HBSMs and FBSMs is reduced enormously. Besides, the thermal control strategy does not bring negative influence on the steady-state output performance of hybrid MMC. Finally, the theoretical analysis and effectiveness of the proposed control methods are verified based on a laboratorial MMC prototype.

This paper presents a practical strategy for utilizing the submodule (SM) redundancy of a modular multilevel converter (MMC) for its fault tolerance. This strategy provides a systematic framework for balancing the tradeoff between two conventional methods for using the active redundancy and, thus, achieves operational flexibility. One of the existing methods improves SM reliability owing to less voltage stress on the SM components by employing all of the SMs to form the ac or dc voltages (voltage-sharing mode). The other avoids transients by keeping the average SM voltage constant at the cost of slightly increased stress on the SM components (fixed-level mode), which, however, can be controlled to provide the grid-adaptive operation by reserving the energy of the SMs not in service. We, thus, develop a new redundancy management scheme by integrating these two methods and exploiting their technical benefits to meet the PQ requirements and MMC control performance. This research provides a theoretical basis and a technical guide to determining the number of SMs, which can further increase the voltage steps as per the MMC and grid conditions. This paper also connects the remaining PQ capability of the MMC at a particular operating point with the SM redundancy concept by defining a potential redundancy, especially useful when the physical redundancy is exhausted. The theoretical findings and efficacy of the proposed strategy are validated through PSCAD/EMTDC time-domain simulations followed by experiments using a nine-level single-phase MMC system.