Comparing analytical modeling with simulation for network processors: a case study

SummaryMulticore network processors have been playing an increasingly important role in computational processes, which emphasize on scalability and parallelism of the systems, in distributed environments especially in Internet‐based delay‐sensitive applications. It is an important but unsolved issue, however, to efficiently schedule tasks in network processors with multicore and multithread for improving the system throughput as much as possible. Profiling can gather runtime environment information and guide the compiler to optimize programs through scheduling tasks based on the runtime context. This paper proposes a profiling‐based task scheduling approach, targeting on improving the throughput of multicore network processor (Intel IXP) systems in the balanced pipeline way. In this work, we investigate a profiling‐based task scheduling framework, a task scheduling algorithm, and a set of performance models. Our task allocation scheme maps tasks onto the pipeline architecture and multiple threads of network processors in parallel, which incorporates the profiling context and global thread refinement. We evaluate our task scheduling algorithm by implementing representative network applications on the Intel IXP network processor. Experimental results demonstrate that our algorithm is able to schedule tasks in a balanced pipeline fashion and achieve the high throughput and data transmission rate. Copyright © 2012 John Wiley & Sons, Ltd.

Chapter 2 - Benchmarking Network Processors

Network processors (NPs) typically contain multiple concurrent processing cores. State-of-the-art programming techniques for NPs are invariably low-level, requiring programmers to partition code into concurrent tasks early in the design process. This results in programs that are hard to maintain and hard to port to alternative architectures. This paper presents a new approach in which a high-level program is separated from its partitioning into concurrent tasks. Designers write their programs in a high-level, domain-specific, architecturally-neutral language, but also provide a separate Architecture Mapping Script (AMS). An AMS specifies semantics-preserving transformations that are applied to the program to re-arrange it into a set of tasks appropriate for execution on a particular target architecture. We (i) describe three such transformations: pipeline introduction, pipeline elimination and queue multiplexing; and (ii) specify when each can be safely applied.As a case study we describe an IP packet-forwarder and present an AMS script that partitions it into a form capable of running at 3Gb/s on an Intel IXP2400 Network Processor.KeywordsGlobal VariableConcurrent TaskConcurrent ProgramSource ProgramTarget ArchitectureThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Network processors in general, enable us to add, through software, the latest-and-greatest network services while maintaining high packet throughput and low packet latency. Simply put, the network processors offer performance and flexibility for implementing network service. IPSec is a set of protocols developed by the IETF to support secures exchange of packets at the IP layer. This paper describes the design of an IPSec application using the Intel IXP2400 network processor. The application described in this paper is supported on the Intel IXDP2400 advanced development platform

We introduce advanced techniques to develop embedded real-time controllers for networking applications using a Modeling and Simulation (M&S) based methodology. Our solution relies on the DEVS formalism and the Embedded CD++ (ECD++) real-time simulator. We show how DEVS-based prototypes can be embedded in the target hardware, consisting of an Intel IXP2400 Network Processor. We developed interface libraries allowing DEVS models to interact with specialized microcontrollers for high performance packet handling. We also introduce a portable Virtual Lab for developing prototypes and deploying them for quick validation on a real-world network. Our approach provides model continuity, eliminating the need for adapting logic or structure of the controllers when evolving from standalone simulations to execution in the target platform.

Advancements in silicon photonics technology are enabling large scale integration of electro-optical circuits and systems. To fully exploit this potential, automated techniques for design space exploration and physical synthesis for integrated optics must be developed. This paper investigates how conventional VLSI physical design automation techniques can be adapted for integrated optics applications. We present an overall methodology for cell-placement, global routing, and detail routing for physical synthesis of optical circuits. In addition, we highlight optics-specific constraint models, design rules and optimization criteria that will have to be accounted for in physical design automation.

Designing the next‐generation complex distributed cyber‐physical systems (dCPS) poses significant challenges for manufacturing companies, necessitating efficient design space exploration (DSE) techniques to evaluate potential design decisions and their impact on nonfunctional aspects of the systems, such as performance, reliability and energy consumption. This paper introduces CompDSE, a methodology designed to facilitate the DSE of complex dCPS, specifically focusing on the cyber components, that is, the computing subsystems within dCPS. CompDSE defines and utilises abstract models of the application workload, computing hardware platform and workload‐to‐platform mapping of dCPS, automatically derived from runtime trace data, and integrates them into a discrete event simulation environment to explore various design points. We demonstrate the effectiveness of our methodology through a case study on the ASML TWINSCAN lithography machine, a complex industrial dCPS. The results showcase potential performance enhancements achieved by optimising computing subsystems while considering physical constraints. Evaluating each design point takes under a minute, highlighting the CompDSE efficiency and scalability in tackling complex dCPS with large design spaces.

Explicit congestion control schemes use router feedback to overcome limitations of the standard mechanisms of the Transmission Control Protocol (TCP). These approaches require additional packet processing in every router and therefore raise the question whether, and how, this can be achieved in high-speed routers. This paper investigates the realization complexity of these router functions of two such schemes, the TCP Quick-Start extension and the Explicit Control Protocol (XCP). Our focus lies on the implementation using a network processor. We show that synchronization issues among parallel processing entities have to be considered, and that this affects the router performance. We develop and compare different synchronization mechanisms for highly parallel packet processing. Our prototype implementation on an Intel IXP network processor allows to quantify the impact on throughput and delay caused by the additional packet processing in the fast path. The measurements reveal that Quick-Start and XCP processing is feasible at multiple Gbit/s line speed, with Quick-Start being simpler to scale. We expect similar results for the implementation of the Rate Control Protocol (RCP), which is another router-assisted congestion control scheme, requiring no elaborate synchronization. Finally, we study the implementation using programmable logic and show the applicability of XCP and in particular Quick-Start even at significantly higher line speeds.

We present an architecture for Distributed Controllable Networks (DCN) which provides distributed control and management functions to networks. This control system can collect and correlate network information between several manageable nodes placed at different locations in the network to offer a large scale view to the network operator. Also, this system can deploy management program and commands to the manageable nodes to control the whole network. The system is capable of capturing packets and pre-processing them on the node itself and the more detailed analysis is taken place in a distributed way. The prototype implementation of our system is based on Intel IXP2400 network processor.

Chapter 13 - Intel Corporation—Intel IXP2400 Network Processor: A Second-Generation Intel NPU

The evolution towards IP-aware access networks creates the possibility (and, indeed, the desirability) of additional network services, like firewalling or NAT, integrated into the network devices. These new services, however, force the network components to be both flexible (to cope with changing protocols and applications) and powerful. Network processors as a platform on which to implement the network services seem to fit the bill.System performance should be assured by incorporating performance analysis into the design of the system, by means of performance modeling at the architectural design stage. This paper describes the use of Software Performance Engineering during the design of a firewall/NAT router on the Intel IXP2400 network processor. Several design options were first modeled and analysed, and based on those simulations, a final design was chosen and implemented.

With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of network processors. In this paper, we use an assertion-based methodology for system-level power/performance analysis to study two dynamic voltage scaling (DVS) techniques, traffic-based DVS and execution-based DVS, in a network processor model. Using the automatically generated distribution analyzers, we analyze the power and performance distributions and study their trade-offs for the two DVS policies with different parameter settings such as threshold values and window sizes. We discuss the optimal configurations of the two DVS policies under different design requirements. By a set of experiments, we show that the assertion-based trace analysis methodology is an efficient tool that can help a designer easily compare and study optimal architectural configurations in a large design space.

Installation of subsea pipelines using reeling process is an attractive method. The pipeline is welded in long segments, typically several kilometers in length, and reeled onto a large diameter drum. The pipeline is then transported onto such reel to the offshore site where it is unreeled and lowered on the seabed. The deformation imposed on the pipeline while spooled onto the drum needs to be controlled so that local buckling is avoided. Mitigation of such failure is generally provided by proper pipeline design & reeling operation parameters. Buckling stems from excessive strain concentration near the circumferential weld area resulting from strength discontinuity at pipeline joints, mainly depending on steel wall thickness and yield strength. This requires the characterization of critical mismatches obtained by trial and error. Such method is a long process since each “trial” requires a complete Finite Element Analysis run. Such simulations are complex and lengthy. Occasionally, this can drive the selection of the pipeline minimum wall thickness, which is a key parameter for progressing the project. The timeframe of such method is therefore not compatible with such a key decision. The paper discusses the use of approximation models to capitalize on the data and alleviate the design cost. To do so, design of experiments and automation of the computational tool chain are implemented. It is demonstrated that initial complex chain of FEA computational process can be replaced using design space description and exploration techniques such as design of experiments combined with advanced statistical regression techniques in order to provide an approximation model. This paper presents the implementation of such methodology and the results are discussed.

Design Space Exploration (DSE) techniques for complex embedded systems must cope with a huge variety of applications and target architectures as well as a wide spectrum of objectives and constraints. In particular, existing design automation approaches are either problem-independent, in that they do not exploit any knowledge about the optimization problem at hand, or are tailored to specific a priori assumptions about the problem and/or a specific set of design objectives. While the latter are only applicable within a very limited scope of design problems, the former may struggle to deliver high-quality solutions for problems with large design spaces and/or complex design objectives. As a remedy, we propose Importance-Guided Order Rearrangement (IGOR) as a novel approach for DSE of embedded systems. Instead of relying on an a priori problem knowledge, IGOR uses a machine-learning-inspired technique to dynamically analyze the importance of design decisions, i.e., the impact that these decisions—within the specific problem that is being optimized—have on the quality of explored problem solutions w.r.t. the given design objectives. Throughout the DSE, IGOR uses this information to guide the optimization towards the most promising regions of the design space. Experimental results for a variety of applications from different domains of embedded computing and for different optimization scenarios give evidence that the proposed approach is both scalable and adaptable, as it can be used for the optimization of systems described by several thousands constraints, where it outperforms both problem-specific and problem-independent optimization approaches and achieves ε-dominance improvements of up to 95%.

Surrogate model based design space exploration (DSE) techniques have been widely used in finding the Pareto-optimal design points of embedded processor architectures. However, existing such methods lack of sound modeling of the uncertainty of the surrogate models, which greatly limits the searching scope. In this paper we propose an expected hypervolume improvement (EHVI) algorithm which models the uncertainty of an adaptive component selection and smoothing operator (ACOSSO) surrogate model by means of constructing a Gaussian random distribution and searches the Pareto points by taking an EHVI criterion. Experimental results prove the effectiveness of the proposed algorithm through comparing with two existing DSE algorithms.