Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache

This article presents the first memory allocation scheme for embedded systems having a scratch-pad memory whose size is unknown at compile time. A scratch-pad memory (SPM) is a fast compiler-managed SRAM that replaces the hardware-managed cache. All existing memory allocation schemes for SPM require the SPM size to be known at compile time. Unfortunately, because of this constraint, the resulting executable is tied to that size of SPM and is not portable to other processor implementations having a different SPM size. Size-portable code is valuable when programs are downloaded during deployment either via a network or portable media. Code downloads are used for fixing bugs or for enhancing functionality. The presence of different SPM sizes in different devices is common because of the evolution in VLSI technology across years. The result is that SPM cannot be used in such situations with downloaded codes. To overcome this limitation, our work presents a compiler method whose resulting executable is portable across SPMs of any size. Our technique is to employ a customized installer software, which decides the SPM allocation just before the program's first run, since the SPM size can be discovered at that time. The installer then, based on the decided allocation, modifies the program executable accordingly. The resulting executable places frequently used objects in SPM, considering both code and data for placement. To keep the overhead low, much of the preprocessing for the allocation is done at compile time. Results show that our benchmarks average a 41% speedup versus an all-DRAM allocation, while the optimal static allocation scheme, which knows the SPM size at compile time and is thus an unachievable upper-bound and is only slightly faster (45% faster than all-DRAM). Results also show that the overhead from our customized installer averages about 1.5% in code size, 2% in runtime, and 3% in compile time for our benchmarks.

Most of the microprocessor spends majority of its time waiting for the data to be transferred from slow memory devices connected to it, resulting in Memory wall problem. The main aim of this paper is to reduce memory wall problem by increasing not only processor speed but also the memory speed. This can be achieved by placing efficient and small memory near the processor so that energy efficiency of the system can be improved. Such memory is called Scratch Pad memory (SPM). Scratch pad memory (SPM) and cache memory plays a vital role in improving the efficiency of the system. Repositioning of code in on-chip and off-chip memory increases the efficient of the utilization of multiprocessing embedded system. Optimal code layout design is developed to place the code in memory for preventing the cache conflicts and misses. Many researchers discussed about the usage of SPM and cache memory to improve the efficiency of the system but combining the both is not done. In this work both SPM and cache memory is combined with the proposed Meta heuristics technique. Meta heuristic model is the proposed model in which along with the SPM, Cache code layout is developed to place the code in it, resulting better performance compared with the other two models namely ILP model and Heuristic model. It is found that the two stage meta-heuristic model yield more efficiency and consume less energy than other two models.

An energy-efficient distributed Scratchpad Video Memory Architecture (dSVM) for the next-generation parallel High Efficiency Video Coding is presented. Our dSVM combines private and overlapping (shared) Scratchpad Memories (SPMs) to support data reuse within and across different cores concurrently executing multiple parallel HEVC threads. We developed a statistical method to size and design the organization of the SPMs along with a supporting memory reading policy for energy efficiency. The key is to leverage the HEVC and video content knowledge. Furthermore, we integrate an adaptive power management policy for SPMs to manage the power states of different memory parts at run time depending upon the varying video content properties. Our experimental results illustrate that our dSVM architecture reduces the overall memory energy consumption by up to 51%-61% compared to parallelized state-of-the-art solutions [11]. The dSVM external memory energy savings increase with an increasing number of parallel HEVC threads and size of search window. Moreover, our SPM power management reacts to the current video properties and achieves up to 54% on-chip leakage energy savings.

To realize a highly efficient embedded system employing an enhanced soft-core processor with SIMD operations, we are developing the MIQS (MIPS Instruction processor with Quadword SIMD extension) system. Generally, in many embedded systems using FPGA and memory devices, relatively low bandwidth restricts memory access performance and the low memory performance limits the system performance even though high-performance operations are implemented on the FPGA device. We introduce a high-performance on-chip memory system on the MIQS system to reduce the number of accesses to the off-chip memory in order to improve the system performance. This paper proposes a highly efficient memory access method using a locked-cache. This paper also discusses implementation issues of the proposed method and extends the instruction set to control the locked-cache. As our preliminary evaluation to estimate the effectiveness of the on-chip memory systems, we run four application programs on two configurations of the MIQS systems, one has scratch pad memory (SPM) and the other one has an ordinal cache, respectively. The results show that the best configuration of on-chip memory varies depending on the application.

In this paper, we propose a data partitioning technique for the memory subsystem that consists of a multi-ported scratchpad memory (SPM) unit and a single-ported data cache in coarse-grained reconfigurable arrays (CGRA) architecture. The embedded reconfigurable processor executes programs by switching between the Non-VLIW and VLIW modes depending on the type of the code region to achieve high performance. The VLIW mode exploits code regions with high ILP that require high memory bandwidth and the Non-VLIW mode exploits those with low ILP that require low memory latency. Our data partitioning technique between the SPM and the data cache is based on data interference graph reduction and profiling information. Given an SPM size, it finds the optimal data partitions by taking the VLIW instruction schedule into consideration. We evaluate our data partitioning technique for the CGRA architecture with three representative multimedia applications.

To better understand how developmental differences impact performance on a broad selection of common physical fitness measures, we examined changes in boys and girls from fourth to fifth grade. Subjects included 273 boys (age, 9.5 ± 0.6 years; height, 139.86 ± 7.52 cm; mass, 38.00 ± 9.55 kg) and 295 girls (age, 9.6 ± 0.5 years; height, 139.30 ± 7.19 cm; weight, 37.44 ± 9.35 kg). We compared anthropometrics, cardiorespiratory and local muscular endurance, flexibility, power, and strength. A mixed-method analysis of variance was used to compare boys and girls at the 2 time points. Pearson correlation coefficients were used to examine relationships between anthropometric and fitness measurements. Significance was set at p ≤ 0.05. Weight increased significantly (>10%) in both sexes, and girls became significantly taller than boys after growing 4.9% by fifth grade (vs. 3.5%). Both groups improved cardiorespiratory endurance and power, although boys performed better than girls at both time points. Boys were stronger in fourth grade, but girls improved more, leading to similar fifth-grade values. Girls were more flexible in fourth grade, but their significant decreases (∼32.4%) coupled with large improvements in boys (∼105%) resulted in similar fifth-grade scores. Body mass index (BMI) was positively correlated with run time regardless of grade or sex. Power was negatively correlated with BMI and run time in fourth grade. In conclusion, sex-specific differences in physical fitness are apparent before pubescence. Furthermore, this selection of measures reveals sexually dimorphic changes, which likely reflect the onset of puberty in girls. Coaches and teachers should account these developmental differences and their effects on anthropometrics and fitness in boys and girls.

Dynamic translation is a general purpose tool used for instrumenting programs at run time. Performance of translated execution relies on balancing the cost of translation against the benefits of any optimizations achieved, and many current translators perform substantial rewriting during translation in an attempt to reduce execution time. Our results show that these optimizations offer no significant benefit even when the translated program has a small, hot working set. When used in a broader range of applications, such as ubiquitous policy enforcement or penetration detection, translator performance cannot rely on the presence of a hot working set to amortize the cost of translation. A simpler, more maintainable, adaptable, and smaller translator appears preferable to more complicated designs in most cases.HDTrans is a light-weight dynamic instrumentation system for the IA-32 architecture that uses some simple and effective translation techniques in combination with established trace linearization and code caching optimizations. We present an evaluation of translation overhead under both benchmark and less idealized conditions, showing that conventional benchmarks do not provide a good prediction of translation overhead when used pervasively.A further contribution of this paper is an analysis of the effectiveness of post-link static pre-translation techniques for overhead reduction. Our results indicate that static pre-translation is effective only when expensive instrumentation or optimization is performed.

Dynamic translation is a general purpose tool used for instrumenting programs at run time. Many current translators perform substantial rewriting during translation in an attempt to reduce execution time. When dynamic translation is used as a ubiquitous policy enforcement mechanism, the majority of program executions have no dominating inner loop that can be used to amortize the cost of translation. Even under more favorable usage assumptions, our measurements show that such optimizations offer no significant benefit in most cases. A simpler, more maintainable, adaptable, and smaller translator may be preferable to more complicated designs. In this paper, we present HDTrans, a light-weight IA-32 to IA-32 binary translation system that uses some simple and effective translation techniques in combination with established trace linearization and code caching optimizations. We also present an evaluation of translation overhead under non-ideal conditions, showing that conventional benchmarks do not provide a good prediction of translation overhead when used pervasively. A further contribution of this paper is an analysis of the effectiveness of post-compile static pre-translation techniques for overhead reduction. Our results indicate that static pre-translation is effective only when expensive instrumentation or optimization is performed, and that efficient reload of pre-translated code incurs a substantial execution-time penalty.

A precise bit-error probability (BEP) analysis method is derived for a multicode direct-sequence code-division multiple-access (DS-CDMA) system in an additive white Gaussian noise channel. The method is applicable to a multicode DS-CDMA system with an arbitrary number of multiple code sequences, and any selection of multiple code sequences. The precise method gives results that discriminate the effect of the selection of different multiple code sequences on the BEP, whereas Gaussian approximations (GAs) do not. Thus, the new method can be used to select the best multicode set for a given system, a task that cannot be achieved using GAs. A two-step analytical procedure enables deriving an explicit, compact form for the CF of the receiver decision statistic in a DS-CDMA system with an arbitrary number of multiple code sequences, and for any selection of multiple code sequences.

MAPE-K/MAPE-SAC: An interaction framework for adaptive systems with security assurance cases

The development of a novel method to estimate the state of charge (SOC) with low read-only memory (ROM) occupancy, high stability, and high anti-interference capability is very important for the battery management system (BMS) in actual electric vehicles. This paper proposes the square root cubature Kalman filter (SRCKF) with a temperature correction rule, based on the BMS of a common on-board embedded micro control unit (MCU), to achieve smooth estimation of SOC. The temperature correction rule is able to reduce the testing effort and ROM space used for data table storage (189.3 kilobytes is much smaller than the storage of the MPC5604B, with 1000 kilobytes), while the SRCKF is adopted to achieve highly robust real-time SOC estimation with high resistance to interference and moderate computing cost (68.3% of the load rate of the MPC5604B). The results of multiple experiments show that the proposed method with less computational complexity converges rapidly (in approximately 2.5 s) and estimates the SOC of the battery accurately under dynamic temperature condition. Moreover, the SRCKF algorithm is not sensitive to the high measuring interference and highly nonlinear working conditions (even with 1% current and voltage measurement disturbances, the root mean square error of the proposed method can be as high as 0.679%).

Vis: Virtualization enhanced live forensics acquisition for native system

Earliest arrival flows capture the essence of evacuation planning. Given a network with capacities and transit times on the arcs, a subset of source nodes with supplies and a sink node, the task is to send the given supplies from the sources to the sink “as quickly as possible.” The latter requirement is made more precise by the earliest arrival property, which requires that the total amount of flow that has arrived at the sink is maximal for all points in time simultaneously. It is a classical result from the 1970s that, for the special case of a single source node, earliest arrival flows do exist and can be computed by essentially applying the successive shortest-path algorithm for min-cost flow computations. Although it has previously been observed that an earliest arrival flow still exists for multiple sources, the problem of computing one efficiently has been open for many years. We present an exact algorithm for this problem whose running time is strongly polynomial in the input plus output size of the problem.

A trip time analyzer is a system for the offline gathering and analysis of transit operations data. The analyzer consists of a location system; an onboard computer that logs events such as doors opening and closing, stamping each event with time and location data; software that interprets the event logs to reconstruct vehicle trajectories; and a database for storing and analyzing historical data. For virtually all trips, a trip time analyzer provides data on running time by segment, schedule and headway deviation by time point, and delay by segment. Providing a high-quality operation requires these types of data. The benefits and capabilities of trip time analyzers are described, using examples from the Trip Time Analysis in Public Transport system in use in Eindhoven, the Netherlands. Those benefits include monitoring operational quality; improving the schedule; diagnosing operational problems and evaluating countermeasures; and supporting operators, the implementation of priority at traffic signals, and research and innovation in operations management. Trip time analyzers are distinct from, but can share many components with, automatic vehicle location systems and automatic passenger counters.

The k shortest simple path problem ( k SSP) asks to compute a set of top- k shortest simple paths from a source to a sink in a digraph. Yen (1971) proposed an algorithm with the best-known polynomial time complexity for this problem. Since then, the problem has been widely studied from an algorithm engineering perspective. The most noticeable proposals are the node-classification (NC) algorithm (Feng, 2014) and the sidetracks-based (SB) algorithm (Kurz, Mutzel, 2016). The latest offers the best running time at the price of a significant memory consumption. We first show how to speed up the SB algorithm using dynamic updates of shortest path trees resulting in a faster algorithm (SB*) with the same memory consumption. We then propose the parsimonious SB (PSB) algorithm that significantly reduces the memory consumption of SB at the cost of a small increase of the running time. Furthermore, we propose the postponed node-classification (PNC) algorithm that combines the best of the NC and the SB algorithms. It offers a significant speed up compared to the SB algorithm while using the same amount of memory as the NC algorithm. Our experimental results on complex networks show that all the considered algorithms have low memory consumption, and that the PSB algorithm is the fastest. On road networks, the relative performances of the algorithms depend on the number k of requested paths. Indeed, when the number k of requested paths is small (i.e., k ≤ 20 in our experiments), the SB* algorithm is the fastest among the considered algorithms, but it suffers from a large memory consumption and it offers very bad performances on some queries. When the number of requested paths is large (i.e., larger than 20 according to our experiments), the PNC algorithm is the fastest among the considered algorithms on road networks and it has a low memory footprint. The PNC algorithm is therefore a better choice on road networks.