Compiler techniques for increasing CU/PE overlap in SIMD machines

The fastest programmable DSP processors are unable to meet the speed requirements of many advanced signal processing applications. SlMD machines have been a preferred solution in such applications because of their inherent spatial parallelism. In such machines, a control unit (CU) broadcasts simple machine instructions simultaneously to a number of processing elements (PEs) executing the same instruction on different data The performance of such architectures can be vastly enhanced if the PEs can execute at the level of signal processing function rather than low level machine instruction. This can be made possible if the PEs are so designed that they can receive and execute functional level instruction from the CU instead of simple machine level instruction. FPGAs have emerged as high performance flexible hardware for many signal processing applications but they are not optimised for any particular application. Hence, they can not offer highest possible performance at lowest silicon cost for a given signal processing algorithm. This paper addresses these issues by introducing a new reconfigurable DSP processor, "single function multiple data (SFMD)" which eliminates the drawbacks of conventional SIMD machines and offers a balance between flexibility, reconfiguration latency and performance

Computer architectures are expected to change to support Exascale computing in the near future. As energy and cooling constraints limit increases in microprocessor clock speeds and number of cores, computer companies are turning to parallel programming. Nowadays, parallel programming is achieved by increasing the number of processing elements in processor cores, increasing the number of processor cores itself and complicated parallel programming where programmer has the responsibility of allocating memory and synchronizing the communication between the processing elements as well as processor cores. It becomes increasingly difficult and expensive to design and produce shared memory machines with ever increasing number of processors. Increase in the number of processors is a major disadvantage when it comes to energy consumption. In this work, we present a new architecture for processor design based on pairwise balanced combinatorial interconnection of processing and memory elements. The proposed processor uses two operand instructions, so that the set of executable machine instructions is partitioned by these pairs. This kind of partition allows parallel processing of data-independent instructions. Since this partition is done at the compile time, the architecture extracts the instruction level parallelism without run-time overheads. We analyze and confirm the performance improvements through simulations. The suggested combinatorial arrangement gives set of architectures with various degrees of performance enhancement.

The microprocessor industry has been striving hard to keep pace with Moore's law. Two of the principal problems have been the interconnect delay and wiring density. This paper presents a new and efficient design, implementation of an array of single bit optical RISC processors, which demonstrates the distribution of data through integrated CMOS photodetector and photoreceiver circuit. The CASPR chip incorporates an Instruction Fetch Unit (IFU) to fetch the instructions from a host computer. The Processing Element uses the stream of instructions to perform the necessary calculations. The IFU determines the branching of the instruction and gives the instructions in the correct sequence to the Processing Element. Each Processing Element (PE) consists of its Control Unit, Data path, ALU and Memory Register Bank. Communication between the PEs is effected by using nearest neighbor communication. The principal advantage of our design is that the user can decide what applications the chip needs to be used for and how. The final chip would comprise of a 4 /spl times/ 4 array of PEs with a single IFU interfacing with the host computer.

Cloud services are one of the most quickly developing technologies. Furthermore, load balancing is recognized as a fundamental challenge for achieving energy efficiency. The primary function of load balancing is to deliver optimal services by releasing the load over multiple resources. Fault tolerance is being used to improve the reliability and accessibility of the network. In this paper, a hybrid Deep Learning-based load balancing algorithm is developed. Initially, tasks are allocated to all VMs in a round-robin method. Furthermore, the Deep Embedding Cluster (DEC) utilizes the Central Processing Unit (CPU), bandwidth, memory, processing elements, and frequency scaling factors while determining if a VM is overloaded or underloaded. The task performed on the overloaded VM is valued and the tasks accomplished on the overloaded VM are assigned to the underloaded VM for cloud load balancing. In addition, the Deep Q Recurrent Neural Network (DQRNN) is proposed to balance the load based on numerous factors such as supply, demand, capacity, load, resource utilization, and fault tolerance. Furthermore, the effectiveness of this model is assessed by load, capacity, resource consumption, and success rate, with ideal values of 0.147, 0.726, 0.527, and 0.895 are achieved.

Designing a low power Wireless Sensor Network (WSN) Node is highly important for getting longer lifetime. Radio transmission and data processing are energy consuming processes. No compensation can be done in the field of energy consumption in radio transmission. This paper concentrates on energy reduction in the field of On the node processing. Due to limited energy supply from batteries the node must trade communication for on the node computation. Many of the WSN data processing algorithms use parallel prefix operations as common denominator. Parallel Prefix Operations have the form of Binary Tree Architecture. Binary tree architecture uses more number of Processing Element (PE) s. Parallel Prefix operations using Binary Tree Architecture (BTA) uses more area and more power. Binary Tree Architecture can be modified in to area and power efficient Folded Tree Architecture (FTA). A Digital comparator is a hardware electronic device that has two binary inputs and determines whether one number is greater than, less than or equal to the other number. The comparators are widely used in Micro Controller Units (MCUs) of WSN nodes. This is a crucial data path element of image and signal processing architectures. By using Folded Tree Architecture Area and Power Efficient Comparator Architecture can be formed. Thus Power and Area efficient WSN node can be formed.

Many loop nests in scientific codes contain a parallelizable outer loop but have an inner loop for which the number of iterations varies between different iterations of the outer loop. When running this kind of loop nest on a SIMD machine, the SIMD-inherent restriction to single program counter common to all processors will cause a performance degradation relative to comparable MIMD implementations. This problem is not due to limited parallelism or bad load balance, it is merely a problem of control flow.This paper presents a loop transformation, which we call loop flattening, that overcomes this limitation by letting each processor advance to the next loop iteration containing useful computation, if there is such an iteration for the given processor. We study a concrete example derived from a molecular dynamics code and compare performance results for flattened and unflattened versions of this kernel on two SIMD machines, the CM-2 and the DECmpp 12000. We then evaluate loop flattening from the compiler's perspective in terms of applicability, cost, profitability, and safety. We conclude with arguing that loop flattening, whether performed by the programmer or by the compiler, introduces negligible overhead and can significantly improve the performance of scientific codes for solving irregular problems.

The allocation of the computational load across different processing elements is an important issue in parallel computing. Indeed, an unbalanced load distribution can strongly affect the performances of a parallel system caused by an excess of synchronization idle times due to less loaded processes waiting for more loaded ones. In this article, we focus on the load balancing issues in the context of the parallel execution of spatial-related applications where the domain space is partitioned in regions that are assigned to different processing elements. In particular, without loss of generality, we consider the well-known spatial-related Cellular Automata computational paradigm for evaluating the proposed dynamic load balancing approach. The main contribution of this article is the derivation of simple closed-form expressions that allow to compute the optimal workload assignment in a dynamic fashion, with the goal of guaranteeing a fully balanced workload distribution during the parallel execution. Based on these expressions, an algorithm for balanced execution of cellular automata is presented and implemented using the MPI technology. Eventually, an experimental section practically shows the behaviour of the proposed dynamic load balancing approach and proves its performance improvement, compared to the not-balanced version, as witnessed by the appreciable reduction of execution times.

SummaryLoad balancing among the processing elements (PEs) of distributed stream processing system (DSPS) is a key issue in the presence of data skewness. Existing data partitioning schemes for DSPS suffer from the scalability problem and system in‐efficiency. Non‐key based partitioning strategies raise prohibitively high memory overhead for the stateful operations with a large number of keys and high data parallelism, while the key‐based schemes introduce load imbalance for highly skewed data. Predicting the nature of stream data in advance can help to reduce the load imbalance among the PEs of DSPS. For this purpose, the heavy hitter algorithms approximate the hot items of streaming data. However, existing designs suffer from unsatisfied prediction accuracy. In this work, we propose an efficient algorithm to filter hot items in a stream of incoming data. The proposed scheme dynamically monitors the items of a stream and greatly improves the accuracy of estimation by keeping the actual key‐value pair for the frequent items. On one hand, to ensure better load balancing for the skewed data streams, the detected hot keys are directed to more than two PEs randomly from the limited workers. On the other hand, for less frequent keys, the proposed scheme explores the principle of the power of two choices to distribute load. We conduct extensive experiments on both real‐world and synthetic data sets. The results show that the proposed pre‐filtering approach significantly outperforms existing designs in terms of prediction accuracy. The results also show that our design achieves a more balanced load as compared to the existing designs.

Two-level pipelining in processor arrays (PAs) involves pipelining of operations across processing elements (PEs) and pipelining of operations in functional units in each PE. Although it is an attractive method for improving the throughput of PAs, existing methods for generating PAs with two-level pipelining are restricted and cannot systematically explore the entire space of feasible designs. In this paper, we extend a systematic design method, called General Parameter Method (GPM), we have developed earlier to find optimal designs of PAs with two-level pipelines. The basic idea is to add new constraints on periods of data flows to include the effect of internal functional pipelines in the PEs. As an illustration, we present pipelined PA designs for computing matrix products. For n-dimensional meshes and other symmetric problems, we provide an efficient scheme to obtain a pipelined PA from a non-pipelined PA using a reindexing transformation. This scheme is used in GPM as a pruning condition to arrive at optimal pipelined PAs efficiently. For pipelines with minimum initiation interval (MII) greater than unity, we show additional constraints that ensure correctness of the synthesized PAs.

Discusses the effect of the inter-processor element communication network (IN) on the performance of SIMD machines using discrete event simulation. The performance evaluation process is based on modelling SIMD computer systems composed of a control unit supervising n processing elements (PEs) each having local memory. The PEs communicate with each other through the IN which is assumed to be static throughout the evaluation process. The influence of the IN delay between PEs on the overall system performance such as the speedup, utilization, and throughput is computed. >

Multiprocessor System-on-Chip (MPSoC) based on Network-on-Chip (NoC) integrates a large amount of Processor Elements (PEs) to fulfill the performance requirements of several applications. These applications are composed of a set of intercommunicating tasks, which are dynamically mapped onto PEs of the target architecture. However, the efficient task-mapping requires some previous steps, among them partitioning, which organizes tasks considering their interaction before applying a mapping process. This paper introduces Partition Reduce (PR) — a task partitioning approach based on the MapReduce algorithm targeting homogeneous NoC based MPSoCs. We analyze the efficiency of PR for energy consumption (EC) minimization and load balance (LB). The results obtained from a set of experiments, with large number of tasks, demonstrate that PR is more effective on processing time and result quality when compared to the classic Simulated Annealing (SA). In addition, PR produces partitions with low energy consumption and rigorous load balance.

One class of reconfigurable parallel processing systems is based on the use of a large number of processing elements which can be partitioned into multiple virtual machines. Each virtual machine is controlled by one or more control units. The multiple control units in such a system share a common secondary storage for programs. The control units use paging to transfer programs to their primary memories. One design problem is determining the optimal service rate for the secondary storage of the control units, where the "optimal" is characterized by maximum processor utilization. The PASM parallel processing system is used as a example system to study this problem. The implementation of virtual memory on the PASM control system memory hierarchy is discussed and a queueing network model for the memory hierarchy is developed. Based on assumed values for parameters that characterize the expected task environment, an optimal service rate is derived from the model. The values of the parameters in the model can be varied to determine the impact these changes would have on system performance. Simulation results verifying various aspects of the model are presented and the results are generalized.

Developing SPMD applications with load balancing

Global semantic integrity constraints ensure integrity and consistency of data spanning multiple databases. In this paper, we take initial steps towards representing global semantic integrity constraints for XML databases. We also provide a general framework for checking global semantic integrity constraints for XML databases. Furthermore, we set forth an efficient algorithm for checking global semantic integrity constraints across multiple XML databases. Our algorithm is efficient for three reasons: (1) the algorithm does not require the update statement to be executed before the constraint check is carried out; hence, we avoid any potential problems associated with rollbacks, (2) sub constraint checks are executed in parallel, and (3) most of the processing of algorithm could happen at compile time; hence, we save time spent at run-time. As a proof of concept, we present a prototype of the system implementing the ideas discussed in this paper.

An oil/water, 3-D fully implicit Reservoir Simulator has been implemented on the ICL Distributed Array Processor (DAP), by a joint BNOC/ICL project team. The DAP is a single instruction, multiple data stream machine with 4096 processors in parallel. The major computational areas of code have been implemented on the DAP, leaving I/O and well calculations as serial code on the host 2976 machine. Matrix assembly is inherently parallel and can be implemented easily and efficiently on the DAP with compact code. Table look-up, though not obviously parallel, has been coded using a very efficient parallel algorithm. The Linear Solver, of Line Gauss-Seidel type, has been chosen for its efficiency on the DAP, with odd and even reduction used for solution of the resulting tri-diagonal equations. Further research will be undertaken to increase the robustness of this solver. The initial implementation has a 1-1 mapping of active grid blocks to processors, thus allowing up to 4096 active grid blocks. It is planned to extend to much larger models, and to 3 phase.