Complementary Resistive Switch-Based Smart Sensor Search Engine

Deep packet inspection (DPI) technology has conventionally been introduced for traffic monitoring, bandwidth control, bandwidth allocation, access control of specific types of traffic, etc. By installing a DPI equipment at any arbitrary point in a network, it is possible to monitor communications of many servers simply and this could simplify dramatically the conventional work load for system management and reduction of power consumption by servers. As a new potential application of DPI technology, this paper explores the possibility of applying DPI technology to server congestion control and reduction of power consumption by servers, and presents implementation examples of these applications. This paper first proposes an example of server congestion control method, in which the DPI equipment estimates the CPU usage of each server by constantly monitoring the number of live TCP connections established by each server, and moves some of virtual machines on the congested server to other servers through remote control timely. Next, this paper proposes an example of reducing power consumption by servers, in which the DPI equipment constantly monitors the traffic sent or received in each area with multiple servers. Finally, the feasibility of the proposed methods is demonstrated by an evaluation system with a real DPI equipment.

In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35µm CMOS process. It consumes 5.8mW at 100MHz with a single 3.3V power supply.

This paper presents a new programmable frequency divider designed to generate any integer division of a parent clock frequency. We first introduce a new mathematical expression for the desired output clock period, which forms the basis of our proposed VLSI architecture. This architecture, primarily comprising two parallel comparators and counters, is inherently area-efficient and accurately handles the fractional component of frequency division. The proposed VLSI architecture has been successfully prototyped on a Basys-3 Field Programmable Gate Array (FPGA) board. Measured results demonstrate that the design generates output clock frequencies with a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{5 0 \%}$</tex> duty cycle for even division ratios and a duty cycle between 40 % and 50 % for odd division ratios. The FPGA implementation utilizes 88 LUTs and 59 slice registers, achieving a maximum operating frequency of 118.23 MHz. Furthermore, the suggested VLSI architecture has been Application Specific Integrated Circuit (ASIC) synthesized and post-layout simulated in a 40 nm CMOS process. This ASIC implementation resulted in a compact core area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1103 \mu ~\mathrm{m}^{2}$</tex>. The design consumes 0.839 mW of power while operating at its maximum clock frequency of 1 GHz. A comparison with state-of-the-art implementations reveals that our proposed design achieves an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{8 9. 4 3 \%}$</tex> reduction in area and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{3 2. 7 7 \%}$</tex> reduction in power consumption.

Metal Oxide Thin Film Transistors (MO TFTs) have garnered considerable interest in emerging Internet of Things (IoT) fields such as wearable electronics, displays, Radio Frequency Identification (RFID), and biomedical monitoring, owing to their flexibility and transparency. However, limitations in channel materials make MO TFT-based circuits unipolar. Unipolar circuits often exhibit elevated short-circuit power consumption, which restricts the development of MO TFTs in the IoT sector. This paper introduces a Capacitively Coupled Near-Threshold Biasing (CCNB) technique that leverages the unique Capacitance-Voltage (C-V) characteristics of MO TFTs to bias devices in the near-threshold region, achieving nearly a 95% reduction in power consumption compared to traditional designs with the device coupling ratio (channel capacitance/overlap capacitance) at 40. Furthermore, considering the significance of clock signals in IoT applications, we have also developed a low-power full-swing Ring Oscillator (RO) based on our CCNB technique, resulting in a 90% reduction in power consumption and a nearly 70% reduction in PDP compared to conventional low-power designs.

In this article, six structures/combinations of vertical-channel-FETs (VFETs) were optimized and performance comparison with lateral-gate-all-around (LGAA) FETs and complementary FET (CFET) was made in the advanced applications across device and circuit levels. To find the main resistive and capacitive parasitic, we introduce a novel decomposition methodology for classifying key gate capacitance components. Building on these insights, we propose two optimization strategies: an inner-spacer release technique for overlap capacitance reduction in VFETs and an additional trim-etch method to mitigate resistances. The optimal gate length is also discussed considering the unique channel arrangement of VFETs. Furthermore, we presented a standard cell layout for VFETs, which was used to make direct comparisons of performance–power–area (PPA) with lateral-channel-FETs (LFETs) for 103-ring oscillator (103RO) configurations. Compared to CFET, our simulation results demonstrate that dual-channel complementary stacked VFET (dCVFET) can increase the frequency by 4.4% in iso-power and decrease power by 12.9% in iso-frequency while reducing the area by 4.1%. Compared to LGAA, dual-channel single-layer VFET (dSLVFET) achieves a 14% speed improvement or a 30.7% reduction in power consumption while also reducing the area by 20%. When adopting wrap around contact (WAC), VFETs normally outperform LFETs by achieving nearly a 16% improvement in speed or a 40% reduction in power consumption under the same area.

In this study, we consider the problem of synthesising custom networks-on-chip (NoC) architectures that are optimised for a given application. Both unicast and multicast traffic flows are considered in the input specification. We formulate the joint multicast routing and network design problem using a rip-up and reroute procedure, where each multicast routing step is formulated as a minimum directed spanning tree problem, and we propose a very efficient algorithm called Ripup-Reroute-and-Router-Merging (RRRM). Our new formulation adopts a rip-up and reroute concept that provides us with a heuristic iterative mechanism to identify increasingly improving solutions. The minimum directed spanning tree formulation efficiently captures the best routing solutions for multicast flows during the topology synthesis procedure. Our design flow integrates floorplanning, and our solutions consider deadlock-free routing. Experimental results compared with our previous proposed algorithms CLUSTER and DECOMPOSE on a variety of NoC benchmarks showed that our new synthesis results are largely improved. RRRM can on average achieve a 9% reduction in power consumption over CLUSTER and a 17% reduction in power consumption over DECOMPOSE with 1786× and 57× faster execution times than CLUSTER and DECOMPOSE, respectively. Improvements in performance were also achieved, with an average of 3% reduction in hop counts over CLUSTER and 7% in hop counts over DECOMPOSE on all benchmarks.

Most modern digital receivers sample the received RF signal at an intermediate frequency (IF), then downconvert to the baseband in the digital domain. The baseband samples are subsequently correlated with a time-limited square pulse, which is readily implemented as an integrator. Since correlation is performed at the sampling frequency, the receiver correlates at an unnecessarily high frequency. This high frequency results in significant power dissipation especially if parallel correlators are employed. By downsampling after appropriate filtering to slightly above the signal Nyquist rate, correlation is achieved at a fraction of the sampling frequency, resulting in corresponding reduction in power consumption. Furthermore, by resampling to an integer number of samples per chip, architectural changes in the correlators are possible, allowing even more reduction in power consumption. In this paper, a resampling correlator with minimal hardware overhead that outperforms the conventional correlator is presented.

Design of unbalanced ternary counters using shifting literals based D-Flip-Flops in carbon nanotube technology

Objectives: Processors are computing elements of most of the embedded systems. As the technology is growing day by day, processors that are released in the market are mostly embedded processors. Processors are designed to perform concurrent operations and execution at a higher clock rate to meet the performance demands result in large heat dissipation and energy consumption. Thus there is an emphasis on power and energy consumption reduction in real time embedded processors. This work targets to reduce the processor power consumption without violating the real time constraints. Method: In this work, a dynamic power management technique named dynamic counters is employed in real-time system to minimize power consumption. The proposed method facilitates bounding of the events conservatively for effective bounding of future workload. It also employs scheduling ON and OFF time of the devices based on workload bounding at run-time. Simulation analysis is carried out to confirm the performance enhancement of the proposed method. Findings: Energy consumed by the processor increases with the number of event arrivals and switching of modes facilitates significant energy savings. Improvement: Run-time and memory overheads are overcome by dynamic counter technique. Effective bounding of future workload enhances computational efficiency.

The drive for ultra efficient and low-cost portable devices continues to push the need for low power circuit designs. The increasing transistor density and complexity of IC designs aggravates the task of producing efficient low power and low cost design. The short time to market (TTM) also increases this burden on designers, as optimal designs have to be produced in an ever decreasing amount of time. This paper presents an optimization design flow methodology that optimizes the power (accounting leakage) consumption of integrated circuits (ICs). The design flow incorporates a stochastic gradient descent (SGD) based algorithm and is implemented using a 45 nm thermal sensor circuit as case study. Power-efficient high-sensitive thermal sensors are important to reduce the burden on the systems or circuits that they are implanted to sense. Experiments are performed to apply the proposed design flow methodology on the thermal sensor with the power consumption as the design objective while keeping the temperature resolution as a constraint. Experiments on full-blown (RCLK) netlist of sense amplifier show a reduction in power consumption by 38%.

Recent years have seen an exponential rise in complex software-driven functionality in vehicles, leading to a rising number of electronic control units (ECUs), network capabilities, and interfaces. These expanded capabilities also bring-in new planes of vulnerabilities making intrusion detection and management a critical capability; however, this can often result in more ECUs and network elements due to the high computational overheads. In this paper, we present a consolidated ECU architecture incorporating an Intrusion Detection System (IDS) for Automotive Controller Area Network (CAN) along with traditional ECU functionality on an off-the-shelf hybrid FPGA device, with near-zero overhead for the ECU functionality. We propose two quantised multi-layer perceptrons (QMLP's) as isolated IDSs for detecting a range of attack vectors including Denial-of-Service, Fuzzing and Spoofing, which are accelerated using off-the-shelf deep-learning processing unit (DPU) IP block from Xilinx, operating fully transparently to the software on the ECU. The proposed models achieve the state-of-the-art classification accuracy for all the attacks, while we observed a 15x reduction in power consumption when compared against the GPU-based implementation of the same models quantised using Nvidia libraries. We also achieved a 2.3x speed up in per-message processing latency (at 0.24 ms from the arrival of a CAN message) to meet the strict end-to-end latency on critical CAN nodes and a 2.6x reduction in power consumption for inference when compared to the state-of-the-art IDS models on embedded IDS and loosely coupled IDS accelerators (GPUs) discussed in the literature.

Power consumption is one of the leading producers of Greenhouse Gases and improving it will support Petroleum Development Oman (PDO) to meet its target of net-zero emissions. In 2020, PDO operations emitted tons of CO2 with the highest quantity coming from X field where High Voltage pumps, which consume about 15MW resulting in 75,000 tons of CO2 emissions per year, are used. This paper will discuss the approach used to investigate and solve the given problem. The six-Sigma methodology was used to investigate the high-power consumption in water injection and deep-water disposal processes. Pareto analysis, which was used to scope the project, showed that 35% of power consumption is related to High Voltage injection pumps. The historical data of the response (power consumption) and potential causes of the problem were gathered from the field database. Minitab, a statistical data analysis software, was used in this problem investigation in addition to other Six-Sigma methods including process capability, hypothesis testing, and control charts. Graphical and statistical tools were also used to examine the relationship between the response and variables. Process mapping identified 27 potential causes of higher power consumption in five High Voltage pumps. The historical data of the variables were statistically correlated to measure the strength of the relationship with the response. The analysis concluded that suction pressure for pumps 1510 and 1520 is the statistically significant cause of higher power consumption. The power consumption of these two pumps was directly linked to the suction pressure using the Pearson coefficient factor and p-value. The suction pressure was too low which caused the pumps to consume more energy to pressurize water. Hypothesis testing resulted in a p-value of 0.00, confirming a strong relationship between power consumption and suction pressure. Appropriate countermeasures were developed, and a new pump operation philosophy was implemented, whereby one pump is always kept on standby. This resulted in a 4MW reduction in power consumption and, ultimately, prevented the emission of 18,000 tons of CO2 annually. Other benefits to date include a saving of around $2.6 million per year, with the potential to save more through replication. Additional yet unquantified benefits include curbing the impacts of climate change on the environment. The Six Sigma statistical approach is used to understand the hidden causes of the increase in power consumption that result in higher CO2 emissions. The reduction of power consumption in PDO's X field has paved the way for 10 other projects in the Company to reduce their CO2 emissions. We can partner with other operators in the Sultanate of Oman to follow Petroleum Development Oman's example of using the Six Sigma approach in Energy Transition.

Today, Content Addressable Memory (CAM) is used in a variety of applications, especially such as network routers. Because network routers need high speed, CAM is using NOR type rather than NAND type. However, due to frequent discharge of match line (ML), the power consumption of NOR type CAM is considerable. In this paper, we propose a low power NOR CAM using folded ML and charge recycling. The folded ML structure can reduce the ML voltage swing, and charge recycling can save pre-charge power, so the power consumption of the proposed CAM can be reduced. This proposed CAM has about 75.3% power consumption saving effect compared to conventional NOR type CAM assuming a network router application.

Increased power consumption is a critical concern for smartphone users. While multi-core processors in smartphones have already emerged in market, current applications are yet to take full advantage of this new architecture, particularly in the area of managing power consumption. This paper addresses the issue of managing power consumption in multicore smartphones via a middleware layer that schedules optimal number of cores for currently running applications taking into account the tradeoff between power consumption, performance and user experience. The paper first describes a simple and accurate method to measure the overall power consumption and then studies the impact of scheduling seven different popular applications over one to four cores on the overall power consumption. Based on this study, the paper proposes three new power-aware scheduling algorithms that dynamically schedule optimal number of cores as well as dynamically adjust the voltage frequency of each online core to achieve the best tradeoff between power consumption, application performance and user experience under the current context. Evaluation from a prototype implementation of the middleware on a quad-core HTC One shows that these algorithms result in significant reduction in power consumption while ensuring good performance and user experience.

This paper proposes an adaptive charge sharing (ACS) method for reducing power consumption in liquid crystal displays (LCDs). Our ACS method involves calculating the power consumption of all data lines assuming the charge is shared and analyzing the analog characteristics of the data transitions. With conventional CS, charge is shared between data lines only when the polarities of data signals change. Our ACS method selectively shares charge even when no polarity change occurs, but only if CS provides an overall reduction in power consumption. To compare the performance of ACS and conventional CS, we applied the ACS method to common inversion methods, namely, column, two-dot, and Z inversion. Our simulation results demonstrate that the ACS method can effectively reduce power consumption, especially with the column and Z inversion methods. The average power consumption of the ACS method with column and Z inversion was 87.7% and 84.7%, respectively, of the conventional CS power consumption.