Comprehensive Research of Total Ionizing Dose Effects in GaN-Based MIS-HEMTs Using Extremely Thin Gate Dielectric Layer.

Purpose of WorkRecessed-gate metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) have emerged as a promising technology for normally-off operation because of their ability to withstand high gate voltage sweeps while maintaining low levels of leakage current [1, 2]. Despite their excellent performance, the etch to leave nanometer-thin layers of AlGaN has proven to be a significant challenge due to difficulties in precisely controlling the etching process. Achieving a positive threshold voltage (Vth) while maintaining the high electron mobility characteristic of the two-dimensional electron gas (2DEG) requires atom-level etch control. Additionally, conventional dry etching techniques can potentially cause damage, presenting a second challenge [3]. However, atomic layer etching (ALE) offers a promising solution with its potential for low damage, uniformity, and high-resolution depth control [4]. In this work, we not only focus on the ALE process to leave nanometer-thin layers of AlGaN/GaN as recessed-gate structures but also analyze the breakdown voltage characteristics of the slant-recessed gate structure.ApproachNormally-off AlGaN/GaN MIS-HEMT with a recessed gate structure was fabricated on a 6-inch commercial Si substrate by MOCVD. The process involved mesa isolation by ICP-RIE, followed by the formation of the ohmic contact (Ti/Al/Ni/Au) at 825 °C annealing for source and drain metals, and the AlGaN/GaN recessed gate structure using ALE technology by O2/BCl3 multiple cycles of oxidation and etching [5]. After the recessed-gate process, the native oxide and carbon residue were removed by a wet cleaning process and O2 plasma treatment, and then the atom layer deposition (ALD) of about 12 nm thickness Al2O3 high-dielectric layer was also deposited. The backend process included gate field plate, SiNx passivation, and contact opening. Finally, the Ni/Au metal stack was deposited as pad electrodes, as shown in Fig. 1. The specific characteristics of the fabricated recessed MIS-HEMT were Lg of 3 μm, Lgs of 5 μm, Lgd of 10 μm, and Wg of 100 μm.Results and SignificanceIn Figure 2(a) and (b), TEM profiles of the recessed gate structure were presented. Following the ALE process for the recessed gate structure, the remaining thickness of AlGaN was approximately 5.1 nm and 5.6 nm for Slant A and Slant B, respectively. Although the thickness of AlGaN remaining was similar in both cases, the slant angle of the recessed gate structure differed, significantly. Specifically, Slant A had a 65-degree recessed gate structure, while Slant B had a 45-degree recessed gate structure. In order to analyze of operational characteristics of AlGaN/GaN MIS-HEMT with different slant-recessed gate structures (Slant A and Slant B), the three-terminal OFF-state breakdown voltage (BV) was measured, as shown in Fig. 3. Recessed gate MIS-HEMT feature design of Lg/Lgd/Lgd/Wg of 3/5/10/100 μm, and VG of -10 V was used as this BV measured condition. The Slant B structure demonstrated higher breakdown voltage (BV) performance compared to the Slant A structure. Specifically, the Slant B structure exhibited a BV of 470 V at 1 μA/mm and 750 V at 1 mA/mm, while the Slant A structure had a BV of only 70 V at 1 μA/mm and 140 V at 1 mA/mm. The reason for the superior BV performance of the Slant B structure (45-degree recessed gate structure) was attributed to the gradient of the AlGaN profile, which facilitates the thin film deposition process of materials such as Al2O3 and gate metal (Ni/Au). Additionally, the Slant B structure helps to reduce the high electric field effect between the gate and drain, further contributing to its improved BV performance.[1] Y. S. Lin, Y. W. Lain, and S. S. H. Hsu, "AlGaN/GaN HEMTs With Low Leakage Current and High On/Off Current Ratio," IEEE Electron Device Letters, vol. 31, no. 2, pp. 102-104, 2010.[2] Z. Tang et al., "600-V Normally Off SiNx/AlGaN/GaN MIS-HEMT With Large Gate Swing and Low Current Collapse," IEEE Electron Device Letters, vol. 34, no. 11, pp. 1373-1375, 2013.[3] T. H. Hung, P. S. Park, S. Krishnamoorthy, D. N. Nath, and S. Rajan, "Interface Charge Engineering for Enhancement-Mode GaN MISHEMTs," IEEE Electron Device Letters, vol. 35, no. 3, pp. 312-314, 2014.[4] T. Y. Yang et al., "A Normally-Off GaN MIS-HEMT Fabricated Using Atomic Layer Etching to Improve Device Performance Uniformity for High Power Applications," IEEE Electron Device Letters, vol. 43, no. 10, pp. 1629-1632, 2022.[5] I.-H. Hwang, H.-Y. Cha, and K.-S. Seo, "Low-Damage and Self-Limiting (Al)GaN Etching Process through Atomic Layer Etching Using O2 and BCl3 Plasma," Coatings, vol. 11, no. 3, p. 268, 2021. Figure 1

A silicon nitride (SiNx) film deposited at 500 °C by plasma-enhanced atomic layer deposition (PEALD) is employed as the gate dielectric for GaN-based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). An interface enhancement technology featuring in situ low-damage NH3/N2 remote plasma pretreatments (RPPs) is developed prior to the SiNx gate dielectric deposition, which contributes to an improved surface morphology while remarkably suppressed interface oxides. It is revealed by constant-capacitance deep-level transient spectroscopy that both shallow and deep states at the PEALD-SiNx/III-nitride interface are reduced by about one order of magnitude by the RPP. The in situ RPP and PEALD-SiNx gate dielectric process are implemented into fabrication of enhancement-mode MIS-HEMTs on an ultrathin-barrier AlGaN/GaN heterostructure technology platform. The fabricated MIS-HEMTs deliver an improved threshold stability and maximum output current as compared with devices without the RPP.

Well-suppressed interface states and improved transport properties of AlGaN/GaN MIS-HEMTs with PEALD SiN gate dielectric

In this work, a 100 nm-gate Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /InAlN/GaN metal-insulator-semiconductor high electron mobility transistor (MISHEMT) with a planar nanostrip-channel was fabricated on a Si substrate and its DC, small-signal RF and two-tone intermodulation characteristics were measured. The use of a planar nanostrip-channel and MIS structure allows these devices to have close to 10 dB better intermodulation distortion than traditional InAlN/GaN high electron mobility transistors. In addition, the GaN planar nanostrip-channel MISHEMT shows five orders of magnitude lower gate current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> , 30% higher current drivability and much improved g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> gate voltage swing than a planar nanostrip-channel GaN HEMT with a Schottky gate. This allows the planar nanostrip-channel GaN MISHEMT to be able to operate at higher input gate voltage (more than V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = +4 V) and achieve higher output current with better linearity performance.

Mechanism of leakage of ion-implantation isolated AlGaN/GaN MIS-high electron mobility transistors on Si substrate

The effects of various notch structures on direct current (DC) and radio frequency (RF) performances of AlGaN/GaN high electron mobility transistors (HEMTs) are analyzed. The AlGaN/GaN HEMTs, each with a 0.8-μm gate length, 50-μm gate width, and 3-μm source–drain distance in various notch structures at the AlGaN/GaN barrier layer, are manufactured to achieve the desired DC and RF characteristics. The maximum drain current (I ds,max), pinch-off voltage (V th), maximum transconductance (g m), gate voltage swing (GVS), subthreshold current, gate leakage current, pulsed I–V characteristics, breakdown voltage, cut-off frequency (f T), and maximum oscillation frequency (f max) are investigated. The results show that the double-notch structure HEMT has a 30% improvement of gate voltage swing, a 42.2% improvement of breakdown voltage, and a 9% improvement of cut-off frequency compared with the conventional HEMT. The notch structure also has a good suppression of the current collapse.

III-nitride heterostructure-based metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs), compared with Schottky and p-GaN gate HEMTs, have demonstrated significant potential in the next-generation high-power electronic devices due to their exceptional gate reliability. This study presents a comprehensive investigation of threshold voltage (VTH) instability in III-nitride heterostructure-based MIS-HEMTs, with a specific emphasis on the interfaces of the multi-heterostructures. Two widely studied amorphous materials, namely, Al2O3 and SiNx, have been extensively examined as primary gate insulators in GaN-based MIS-HEMTs. To efficiently remove native oxides from the (Al)GaN surface, a novel in situ high-temperature remote plasma pretreatment (RPP) technique has been developed. This technique involves sequential application of NH3/N2 plasmas on the (Al)GaN surface before depositing the gate insulators using plasma-enhanced atomic layer deposition. The remarkable RPP process has proven to be a highly effective method for revealing atomic steps on the GaN surface, irrespective of whether the surface has undergone oxidation or etching processes. To further enhance the interface quality and potentially reduce bulk traps in the gate insulator, optimization of deposition temperature and post-deposition annealing conditions have been explored. Additionally, an electron-blocking layer, such as SiON, is incorporated into the MIS-HEMTs to prevent electron injection into bulk traps within the insulator. Novel characterization techniques including constant-capacitance and isothermal-mode deep-level transient spectroscopy have also been developed to explore the failure mechanisms in MIS-HEMTs. These techniques allow for the differentiation between bulk traps in the GaN epitaxy and those present within the gate insulators. This in-depth physical understanding provides valuable insights into the sources of failure in GaN-based MIS-HEMTs.

In this study, quaternary InAlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) aimed for power applications were exposed to 800 krad of Co<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{60}~\gamma $ </tex-math></inline-formula>-ray, and their response to total dose effects was recorded. For the irradiation process, devices with five gate-connected field plate schemes of field plate length (without field plate, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2~\mu $ </tex-math></inline-formula> m, 4, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6~\mu $ </tex-math></inline-formula> m, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8~\mu $ </tex-math></inline-formula> m) were tested under either a grounded state or a stressed state. It was discovered that the implementation of the field plate could successfully suppress the virtual gate phenomenon exacerbated by total dose effects. Post-irradiation analysis of the reverse characteristics also revealed that for devices irradiated under a stressed state, field plates could increase the device robustness against total dose effects impacting the electrical breakdown.

In this work, a two-step degradation phenomenon in D-mode Si3N4/AlGaN/GaN metal–insulator–semiconductor-high electron mobility transistors is discussed systematically. During off-state stress, threshold voltage shifts positively for a short duration, and is followed by a negative shift. In contrast, the off-state leakage continues to decrease throughout the entire stress. Results of varied measurement conditions indicate that carrier trapping at different regions dominates this phenomenon. It is interesting that under a large lateral electric field, electron–hole pairs are generated and will then be trapped at the gate dielectric layer. Furthermore, when increasing the stress temperature, impact ionization due to carriers from the gate electrode becomes more severe. Finally, devices with different gate insulator thicknesses are performed to verify the physical model of the degradation behavior.

Trap states at the dielectric/GaN interface of AlGaN/GaN‐based metal–insulator–semiconductor high electron mobility transistors (MIS‐HEMTs) can cause threshold voltage (Vth) instability especially under positive gate bias stress. Herein, the influence of O2 plasma surface preconditioning (SPC) before the atomic layer deposition of the Al2O3 gate dielectric and of N2 postmetallization anneal (PMA) after gate metallization on the Al2O3/GaN interface quality is investigated. The interface is characterized by multifrequency capacitance–voltage measurements which show a smaller frequency dispersion after the employment of SPC and PMA treatments with a reduction of the interface trap density Dit to a value in the order of 2 × 1012 cm−2 eV−1 near the conduction band edge. The effectiveness of SPC and PMA is demonstrated in Al2O3/AlGaN/GaN MIS‐HEMTs by pulsed current–voltage measurements which reveal improved Vth stability.

SiN x deposited by inductively coupled plasma chemical vapor deposition (ICP-CVD) technique at low temperature (70 °C) was investigated as gate dielectric for AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs). Besides significant reduction in gate leakage current, the MIS-HEMTs showed improvement in drain current characteristics, 2DEG channel mobility, $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ ratio, ON-resistance, and three terminal breakdown voltage as compared with reference HEMTs. Very small capacitance–voltage hysteresis (~68 mV) was observed for a gate swing of −10 to +5 V. The effect of SiN x thickness ( $t_{\mathrm {SiN}x}$ ) on the characteristics of MIS-HEMTs was studied. The performance of fabricated MIS-HEMTs was found to be stable for a wide range of temperature.

In this paper, the enhancement-mode operation of the hetestructure of GaN/InN/GaN/In 0.1 Ga 0.9 N of the Metal Insulator Semiconductor High Electron Mobility Transistor (MIS-HEMTs) device having lnN-channel was investigated. The effect of scaling the device dimensions of Metal Insulator, such as the dielectric thickness of HfO 2 and the channel lengths, on the electrical performances was analyzed and compared to the currently used heterostructure. The numerical simulation of synopsis TCAD used showed a significant improvement in the electrical properties of the device that achieved a threshold voltage (V T ) = 0.828 maximum drain current of 1.77 A/mm V, transconductance (g m ) of 2.29 S.mm −1 , lowest ON-state resistance (R ON ) of 0.21 Ω.mm, and along with high-frequency performance achieving f T / f max of 98 GHz/129 GHz and 200 GHz/ 360 GHz respectively. The simulations also showed that this scaled GaN/ InN/ GaN/ In 0.9 Al 0.1 N heterostructure MIS-HEMT is an excellent substitute to the currently used MIS-HEMTs for delivering high power density and frequency at RF/power amplifier applications. Keywords: Enhancement mode, Hydrodynamic simulation, InN channel, MIS-HEMT, In 0.9 Al 0.1 N barrier/buffer, HfO 2 , TCH, Transconductance

The threshold voltage (Vth) instability in GaN-based metal–insulator–semiconductor high-electron mobility transistors (MIS-HEMTs) with 15-nm atomic-layer-deposited (ALD) Al2O3 as gate dielectrics is systematically investigated by dc current–voltage (I–V), high-frequency capacitance–voltage (C–V) (HFCV), and quasi-static C–V (QSCV) characterizations. Both Al2O3/GaN/AlGaN/GaN MIS diode and GaN/AlGaN/GaN Schottky diode only exhibit tiny threshold-voltage hysteresis (ΔVth) (<10 mV) in double-mode (up and down sweep) HFCV characteristics as the maximum forward bias (VFmax) during the sweep is set to 0 V, while an apparent ΔVth (as large as 0.9 V) emerges as VFmax is increased to +5 V for the MIS diode. The stability of Vth in the corresponding MIS-HEMTs is thus studied by increasing the maximum VGS (VGSmax) in the measurement of transfer characteristics. Significant positive Vth shift occurred once the VGSmax exceeds +1 V, while such Vth-instability is still absent in Schottky-gate AlGaN/GaN HEMTs. It is suggested that the acceptor-like deep states at Al2O3/GaN interface account for the Vth-instability in Al2O3/GaN/AlGaN/GaN MIS-HEMTs. As the filling and emission processes of these interface states are slow, they are successfully captured by low-frequency QSCV techniques.

In this work, the conduction mechanisms at the interface of AlN/SiN dielectric stacks with AlGaN/GaN heterostructures have been studied combining different macroscopic and nanoscale characterizations on bare materials and devices. The AlN/SiN stacks grown on the recessed region of AlGaN/GaN heterostructures have been used as gate dielectric of hybrid metal-insulator-semiconductor high electron mobility transistors (MISHEMTs), showing a normally-off behavior (Vth = +1.2 V), high channel mobility (204 cm2 V-1 s-1), and very good switching behavior (ION/IOFF current ratio of (5-6) × 108 and subthreshold swing of 90 mV/dec). However, the transistors were found to suffer from a positive shift of the threshold voltage during subsequent bias sweeps, which indicates electron trapping in the dielectric stack. To get a complete understanding of the conduction mechanisms and of the charge trapping phenomena in AlN/SiN films, nanoscale current and capacitance measurements by conductive atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) have been compared with a macroscopic temperature-dependent characterization of gate current in MIS capacitors. The nanoscale electrical analyses showed the presence of a spatially uniform distribution of electrons trapping states in the insulator and the occurrence of a density of 7 × 108 cm-2 of local and isolated current spots at high bias values. These nanoscale conductive paths can be associated with electrically active defects responsible for the trap-assisted current transport mechanism through the dielectric, observed by the temperature-dependent characterization of the gate current. The results of this study can be relevant for future applications of AlN/SiN bilayers in GaN hybrid MISHEMT technology.

A methodology has been proposed to accurately model the gate stack of Gallium Nitride (GaN) based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). Small-signal analysis has been performed for the device biased in the spill-over region, where electrons accumulate at the insulator/III-Nitride ’critical’ interface. Accounting for the barrier layer resistance with an accurate model yields a near but inexact match between simulation and measurement. It is found that the border trap admittance and the energy distribution of the interface trap capture cross section ( $\sigma $ ) need to be included in order to achieve a very close one. It is concluded that the interface trap density, extracted using conventional small-signal admittance methods, can be significantly off if these non-ideal effects are not incorporated within the equivalent circuit models of GaN-based MIS-HEMTs.