Concurrency Optimization for NIDS (Poster Abstract)

In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a single thread) are issued simultaneously to multiple functional units, and these instructions can begin execution unless there are functional unit conflicts. This parallel execution scheme greatly improves the utilization of the functional unit. Simulation results show that by executing two and four threads in parallel on a nine-functional-unit processor, a 2.02 and a 3.72 times speed-up, respectively, can be achieved over a conventional RISC processor.Our architecture is also applicable to the efficient execution of a single loop. In order to control functional unit conflicts between loop iterations, we have developed a new static code scheduling technique. Another loop execution scheme, by using the multiple control flow mechanism of our architecture, makes it possible to parallelize loops which are difficult to parallelize in vector or VLIW machines.

In this paper, we present the compiler extensions, based on OpenMP libraries, needed for supporting parallel execution on the reconfigurable Molen platform. More specifically, we propose an ILP algorithm to map parallel applications on the target platform, assuming that for a section of the application, the designer can select from a set of hardware implementations with different area and speedup features. Based on profile information, the algorithm aims to minimize the total execution time of the running threads, taking into account the limited reconfigurable area. We show that the speedup of our algorithm compared to other related algorithms is up to 1.9times for a real application and the real hardware implementation of the kernels. We also investigate the impact of several factors such as the size of the reconfigurable area and the number of threads on our algorithm and determine the range of parameters for which the algorithm is efficient.

Defect inspection is a crucial part of industrial manufacturing. However, it relies heavily on human effort on manual visual inspection. Various machine vision techniques have been introduced to replace human labour and to improve inspection quality and efficiency. The limitation of these techniques is that the algorithms need to be engineered again with each different use case. In this work, a Convolutional Neural Network (CNN) is used to classify the defects of the Chemical Mechanical Planarization (CMP) ring. The trained CNN model achieved an accuracy of 91% and the time taken for each inference process is around 1800 msec. To achieve computational efficiency, the CNN model is performed on the embedded device. The previous implementation of embedded CNN deploys OpenCL-based high-level synthesis accelerator on a high-end Field Programmable Gate Array (FPGA) board. In this work, the model inference is accelerated by PipeCNN FPGA implementation on Cyclone-VSE DE1-SoC, a low-end embedded FPGA board. Several configurations of hardware parameters are tested to search for the best setup of the FPGA resources. The hardware implementation has improved approximately seven times faster, as the inference time for each classification has improved from 1800 msec to 250 msec. However, the model implemented using the hardware is observed to produce lower inference accuracy as the accuracy drops from 91% to 81%.

In this paper the experimental validation of a novel, modified double scroll chaotic attractor circuit, employed as a true random binary generator (TRBG) is presented. The double scroll attractor is modeled on Chua's circuit constituted as independent chaotic oscillator using passive only nonlinear device for nonlinear operation leading to chaotic behavior. The output from the chaotic circuit which is a correlated binary sequence is scrambled with a pseudo random binary sequence generator (PRBSG) topology to yield a true random binary source for key stream generation. The modified chaotic circuit has been first modeled in PSpice software. The randomness attributes of the modified generator, obtained from both the PSpice model and hardware implementation, using the PRBSG de-correlator were successfully tested by the well known NIST Test Suite and Diehard Test Set for statistical validation. Output binary streams from the proposed modified generator were examined for randomness using both Test Suites with all tests successfully passed for both PSpice model and experimental chaotic circuit generator. A physical TRBG has been constructed on the basis of the proposed PRBSG modification with all statistical tests successfully passed confirming theoretical expectations. (6 pages)

Process-thread hybrid programming paradigm is commonly employed in SMP clusters. XPFortran, a parallel programming language that specifies a set of compiler directives and library routines, can be used to realize process-level parallelism in distributed memory systems. In this paper, we introduce hybrid parallel programming by XPFortran to SMP clusters, in which thread-level parallelism is realized by OpenMP. We present the language support and compiler implementation of OpenMP directives in XPFortran, and show some of our experiences in XPFortran-OpenMP hybrid programming. For nested loops parallelized by process-thread hybrid programming, it’s common sense to use process parallelization for outer loops and thread parallelization for inner ones. However, we have found that in some cases it’s possible to write XPFortran-OpenMP hybrid program in a reverse way, i.e., OpenMP outside, XPFortran inside. Our evaluation results show that this programming style sometimes delivers better performance than the traditional one. We therefore recommend using the hybrid parallelization flexibly.

The RFID is considered to provide an efficient solution to merge physical world with virtual space for pervasive computing. The wireless sensor network (WSN) is also a feasible and cost-effective candidate for the context sensing in the pervasive computing. We propose a smart space named SmartExhibtion as an scenario where the RFID is integrated to the sensor network and describe the whole architecture together with the application mode. Moreover, we detail the design of the ZigBee-based RFID network for experiment as well as the hardware implementation and the software protocol of the network node - RFSenMote. The characteristic of the paper is that the RFID is extended into sensor network in an actual application scenario and an embedded device which integrates RFID with WSN for the test platform is developed. This integration enables the traits such as self-configuration, random deployment, low-cost and interoperability which are adaptive to the smart space of the pervasive computing. In addition to RFID, the wireless sensor network offers the ability to detect and record contextual changes in the smart environment.

Image data has been generated massively by devices in medical imaging modalities, cameras, and even by artificial intelligence. Encryption is the powerful method to keep the image content confidential, in which an encryption algorithm must include the confusion and diffusion properties. For massive images, a efficient method of encryption must be chosen to meet the demands of encryption speed and confidentiality. So far, chaos-based image encryption has been an active topic of research because it is considered an effective method to remove the correlation in image data as well as to keep confidential by the involvement of chaotic system in the encryption process. Besides, multiple image encryption algorithms encrypt multiple images in parallel, and it provides highly efficient performance in term of speed if it is implemented on a parallel computing platform such as multiple core processing as well as digital hardware design. Chaos-based multiple image encryption is constructed by integrating a chaotic system into multiple image encryption. Recently, many algorithms of chaos-based multiple image encryption have been proposed, and they are proved to have high efficient in terms of both speed and confidentiality. However, all the existing algorithms of chaos-based multiple image encryption require images of the same size and of the same number of bits representing pixels. Further, they encrypt a cohort of plain images at the same time, and all ciphertext images of a cohort must also be decrypted at the same time. It means that if it does not allow to decrypt one or some selected ciphertext images from a cohort separately; and as a result, it wastes time and energy to decrypt unwanted images. In this paper, three novel structures of chaos-based multiple image encryption are proposed which overcome the drawbacks of existing algorithms. That is, the proposed cryptosystems accept cohort images of different sizes; pixels of images can be represented by different numbers of bits; and any selected ciphertext images from a cohort can be decrypted separately. The security is improved by using the session keys of image-content dependency. The proposed structures of multiple image encryption consist of permutation, substitution, and diffusion processes. The difference between three structures is the order of such processes. A perturbed chaotic map and a linear-feedback shift register are employed to generate pseudo-random bit sequences for session keys. The simulation results for the exemplar designs using the proposed structures show the effectiveness by means of the statistical analysis for the session keys using the NIST randomness test, information entropy, histogram, and correlation coefficients of adjacent pixels in ciphertext images, and security analysis by means of space and sensitivity of the secret key. The hardware implementation on the FPGA platform demonstrates the feasibility of the proposed structures by means of throughput and hardware efficiency.

On-board compression systems aim to increase the amount of image data transmitted to ground during a single communication session with the ground station. The adopted approach to lossless image compression employs predictive neural networks, integer wavelet transforms and Peano-Hilbert scan. The performance of these neural networks based techniques has been compared with other lossless compression algorithms such as the Rice Algorithm and JPEG2000. Testing results show that the proposed method outperforms the state-of-theart methods. The focus of the paper is on improving the speed of the neural network component of the image compression algorithm. It is shown that the number of neural networks sets and the size of image tiles affect the processing speed of the neural network predictor. A hardware implementation is proposed which is based on multiple neural processors performing compression of a certain number of image tiles in parallel. It is shown that the proposed hardware implementation can improve significantly the overall speed of the compressor.

Nowadays, many real world problems need fast processing neural networks to come up with a solution in real time. Therefore hardware implementation becomes indispensable. The problem is then to choose the right chip that is to be used for a particular application. For this, a proper set of hardware performance criteria is needed to be able to compare the performance of neural network chips. The most important criterium is related to the speed a network processes information with a given accuracy. For this a new criterium is proposed. The 'effective number of connection bits' represents the effective accuracy of a chip. The '(effective) connection primitives per second' criterium now provides a new speed criterium normalized to the amount of information value that is processed in a connection. In addition to this the authors also propose another new criterium called 'reconfigurability number' as a measure for the reconfigurability and size of a chip. Using these criteria gives a much more neutral view of the performance of a neural network chip than the existing conventional criteria, such as 'connections per second'. >

We present a method to implement trained neural networks on digital programmable hardware. The neural network is trained off-line using a microprocessor system and suitable software. Thereafter the trained neural network is transferred to the hardware implementation. In order to reduce the costs, the network nodes are implemented as multiplexed structures requiring a certain number of clocks for the execution of each iteration. However, in order to increase the overall processing speed the pipelining structure can be also used. It only delays the response with a few microseconds, depending on the clock rate and network complexity. The hardware implementation of neural network using programmable logic devices allows boosting the processing speed, compared to the software implementation, to alternatively reduce the overall costs and provide similar flexibility as the software approach.

Food processing and consumption by herbivores are affected differently by the availability of forage quality and quantity per unit of time. This demonstrates the “Allometric response concept”, and it is considered a significant determinant in habitat use for foraging by grazers. The relevance of this approach has comprehensively been applied to herbivores of different body sizes, but little is known about its demonstration to explain patch use in herbivores with different digestive physiology and body size. We explain the use of patches by grazing herbivores of different digestive physiology and body sizes, Hippopotamus amphibius (hippopotamus, mega non-ruminant) and cattle (ruminant), by integrating foraging relationship herbivores. We analysed the significant relationships between species dropping densities and environmental variables across forty-eight 100 m×100 m plots in Bui National Park, Ghana, during the wet and dry seasons. We found that both species utilised areas closer to the river in the wet season, but the H. amphibius foraged further away from the river during the dry season. Sward height also determined patch use by both species, with the H. amphibius utilising shorter swards than the cattle. Considering the quality of food resources, the study revealed that patch selection of ruminants (cattle) was significantly influenced by nitrogen content. In contrast, acidic detergent fibre content was positively related to non-ruminant species (H. amphibius). The high seasonal effect of sward height and food quality on patch use is primarily due to the species digestive physiology and body size of hippopotamus and cattle at the Bui National Park.

Through most of the evolution of the electronics and computer industry in the twentieth century, technological progress was defined in terms of the inexorable march of density and speed. Increasing density resulted from process improvements that led to smaller and smaller geometries of semiconductor devices, so the number of transistors packed into a given area kept increasing. Increasing processing speed indirectly resulted from the same causes: more processing power on the same chip meant more computation resources and more data storage on-chip, leading to higher levels of parallelism and hence, more computations completed per unit time. Circuit and architectural innovations were also responsible for the increased speed. In the case of processors, deeper pipelines and expanding parallelism available led to improvements in the effective execution speed. In the case of memories, density continued to make remarkable improvements; performance improvements were not commensurate, but nevertheless, architectural innovations led to increased bandwidth at the memory interface.

Reducing energy consumption without affecting computational performance is a significant research driver in computer engineering. The Partitioned Global Address Space (PGAS) programming model provides a global address space for ease-of-use while providing locality-awareness for efficient execution. For symmetric multiprocessor (SMP) clusters, PGAS locality-awareness offers opportunities for intelligent energy management due to the inherent latencies in the interconnection network fabric. In this paper, the second in a series that explores PGAS power optimization, we present a detailed examination of how data locality-awareness can be exploited to improve the energy consumption of workload sharing on SMP clusters. We present a systematic methodology for analyzing a given algorithm's potential for locality-aware power optimization. We show how to automate the code modifications for an iterative stencil loop algorithm using a profiler that analyzes the algorithms' non-local access patterns and optimizes the code for thread-local data pre-fetch. We explore the use of dynamic voltage frequency scaling (DVFS) in conjunction with time-based optimizations and provide an extensible and precise power measurement framework for generating the experimental results. We compare optimized and CPU-default approaches to DVFS application at the program-execution and processor architecture level. We show how the latency of the cluster's interconnection network can impact the opportunities for power optimization by comparing the programs' energy/time behavior when the cluster nodes are connected by Ethernet or Infiniband network fabrics. For our representative iterative stencil loop algorithm, locality aware power optimizations show significant improvements in energy efficiency over native code running in default processor power modes.

Configuration files, command-line arguments and environment variables are the dominant tools for local configuration management today. When accessing such program execution environments, however, most applications do not take context, e.g. the system they run on, into account. The aim of this paper is to integrate unmodified applications into a coherent and context-aware system by instrumenting the getenv API. We propose a global database stored in configuration files that includes specifications for contextual interpretations and a novel matching algorithm. In a case study we analyze a complete Debian operating system where every getenv API call is intercepted. We evaluate usage patterns of 16 real-world applications and systems and report on limitations of unforeseen context changes. The results show that getenv is used extensively for variability. The tool has acceptable overhead and improves context-awareness of many applications.

The growing number of low-power smart devices in the Internet of Things is coupled with the concept of "Edge Computing", that is moving some of the intelligence, especially machine learning, towards the edge of the network. Enabling machine learning algorithms to run on resource-constrained hardware, typically on low-power smart devices, is challenging in terms of hardware (optimized and energy-efficient integrated circuits), algorithmic and firmware implementations. This paper presents FANN-on-MCU, an open-source toolkit built upon the Fast Artificial Neural Network (FANN) library to run lightweight and energy-efficient neural networks on microcontrollers based on both the ARM Cortex-M series and the novel RISC-V-based Parallel Ultra-Low-Power (PULP) platform. The toolkit takes multi-layer perceptrons trained with FANN and generates code targeted at execution on low-power microcontrollers either with a floating-point unit (i.e., ARM Cortex-M4F and M7F) or without (i.e., ARM Cortex M0-M3 or PULP-based processors). This paper also provides an architectural performance evaluation of neural networks on the most popular ARM Cortex-M family and the parallel RISC-V processor called Mr. Wolf. The evaluation includes experimental results for three different applications using a self-sustainable wearable multi-sensor bracelet. Experimental results show a measured latency in the order of only a few microseconds and a power consumption of few milliwatts while keeping the memory requirements below the limitations of the targeted microcontrollers. In particular, the parallel implementation on the octa-core RISC-V platform reaches a speedup of 22x and a 69% reduction in energy consumption with respect to a single-core implementation on Cortex-M4 for continuous real-time classification.