Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform

Handling large-size discrete wavelet transform on network-based computing systems — parallelization via divisible load paradigm

The transformation model plays a vital role in medical image processing. This paper proposed new two Mixed Transforms models that are the hybrid combination of linear and nonlinear Transformations techniques. The first mixed transform is computed in three steps: calculate 2D discrete cosine transform (DCT) of the image, and applying Arnold Transform (AT) on the DCT coefficients, and applying the discrete Wavelet Transform (DWT) on the result to get which was abbreviated as (CAW). The second mixed transform consists of firstly computing the discrete Fourier transform (DFT), net applying the Arnold Transform (AT), and finally, the computation of discrete Wavelet Transform (DWT) which was abbreviated as (FAW). These transforms have superior directional representations as compared to other multiresolution representations such as DWT or DCT and work as non-adaptive mixed transformations for multi-scale object analysis. Due to their relationship to the wavelet idea, they are finding increasing use in areas like image processing and scientific computing. These transforms are tested in medical image classification task and their performances are compared with that of the traditional transforms. CAW and FAW transforms are used in the feature extraction stage of a classification VGG16 deep learning (DNN) task of Tumor MRI medical image. The numerical findings favor CAW and FAW over the wavelet transform for estimating and classifying pictures. From the results obtained it was shown that the CAW and FAW transform gave e much higher classification rate than that achieved with the traditional transforms, namely DCT, DFT and DWT. Furthermore, this combination leads to a family of directional and multi-transformation bases for image processing.

In this paper, a scheme for the design of a high-speed pipeline VLSI architecture for the computation of the 2-D discrete wavelet transform (DWT) is proposed. The main focus in the development of the architecture is on providing a high operating frequency and a small number of clock cycles along with an efficient hardware utilization by maximizing the inter-stage and intra-stage computational parallelism for the pipeline. The inter-stage parallelism is enhanced by optimally mapping the computational task of multi decomposition levels to the stages of the pipeline and synchronizing their operations. The intra-stage parallelism is enhanced by dividing the 2-D filtering operation into four subtasks that can be performed independently in parallel and minimizing the delay of the critical path of bit-wise adder networks for performing the filtering operation. To validate the proposed scheme, a circuit is designed, simulated, and implemented in FPGA for the 2-D DWT computation. The results of the implementation show that the circuit is capable of operating with a maximum clock frequency of 134 MHz and processing 1022 frames of size 512 × 512 per second with this operating frequency. It is shown that the performance in terms of the processing speed of the architecture designed based on the proposed scheme is superior to those of the architectures designed using other existing schemes, and it has similar or lower hardware consumption.

Discrete Wavelet Transform (DWT) has demonstrated advantages in image compression due to its time-frequency resolution property. Dual Tree Complex Wavelet Transform (DTCWT) in addition to the advantages of DWT supports additional properties such as directionality and shift invariant. DTCWT has coefficient redundancy of 4:1 or 2 m :1 in m dimensions thus is four time complex than DWT computation. In this work, DTCWT based image compression algorithm is proposed that performs decomposition using DTCWT and reconstruction is carried out using DWT. The DTCWT bands are companded and encoded using entropy encoder and the quantization of the sub bands introduces minimum loss. The proposed algorithm achieves 77% compression with 40 dB PSNR thus suitable for real time image compression. DTCWT filters are appropriately selected to achieve perfect reconstruction.

In this article, an area-efficient VLSI architecture scheme for high-throughput computation of the 2-D discrete wavelet transform (DWT) is proposed, effectively applied in the context of aircraft cargo hold scenes. The proposed architecture aims to reduce computation and storage resources while maintaining the DWT-IDWT reconstructed image quality for the 9/7 discrete wavelet. The hardware implementation formulae based on the flipping architecture have been modified to reduce RAM storage bit width. By transforming the coefficients of the formula into hardware-friendly values, the required multiplication operations are split into two stages of addition. On this basis, a pipelined architecture is constructed to set the critical path delay (CPD) of the architecture to be close to the delay of a single adder, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{a}$ </tex-math></inline-formula>, thereby achieving a high throughput. Compared to existing architectures in the research field, the proposed single-level 2-D DWT architecture achieves resource savings on the field-programmable gate array (FPGA) platform while ensuring good image reconstruction quality. The advantages of the multilevel 2-D DWT are even more pronounced. In the simulation results on the application-specific integrated circuit (ASIC) platform, the proposed architecture reduces computation time by at least 35.54% while achieving a higher level of decomposition, decreases the area-delay product (ADP) by at least 25.41%, and saves a significant amount of energy per image (EPI). Furthermore, the proposed folded architecture achieves close to 100% hardware utilization efficiency (HUE) in multilevel 2-D DWT computations.

Measurement of the active, reactive, and apparent power is one of the most fundamental tasks of smart meters in energy systems. Recently, a number of studies have employed the discrete wavelet transform (DWT) for power measurement in smart meters. The most common way to implement DWT is the pyramid algorithm; however, this is not feasible for practical DWT computation because it requires either a log N cascaded filter or O (N) word size memory storage for an input signal of the N-point. Both solutions are too expensive for practical applications of smart meters. It is proposed that the recursive pyramid algorithm is more suitable for smart meter implementation because it requires only word size storage of L × Log (N-L), where L is the length of filter. We also investigated the effect of varying different system parameters, such as the sampling rate, dc offset, phase offset, linearity error in current and voltage sensors, analog to digital converter resolution, and number of harmonics in a non-sinusoidal system, on the reactive energy measurement using DWT. The error analysis is depicted in the form of the absolute difference between the measured and the true value of the reactive energy.

One major difficulty in designing an architecture for the parallel implementation of Discrete Wavelet Transform (DWT) is that the DWT is not a block transform. As a result, frequent communication has to be set up between processors to exchange data so that correct boundary wavelet coefficients can be computed. The significant communication overhead thus hampers the improvement of the efficiency of parallel systems, specially for processor networks with large communication latencies. In this paper we propose a new technique, called Boundary Postprocessing, that allows the correct transform of boundary samples. The basic idea is to model the DWT as a Finite State Machine based on the lifting factorization of the wavelet filterbanks. Application of this technique leads to a new parallel DWT architecture. Split-and-Merge, which requires data to be communicated only once between neighboring processors for any arbitrary level of wavelet decompositions. Example designs and performance analysis for 1D and 2D DWT show that the proposed technique can greatly reduce the interprocessor communication overhead. As an example, in a two-processor case our proposed approach shows an average speedup of about 30% as compared to best currently available parallel computation.© (1999) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

This Image compression using Discrete Wavelet Transform has got application in many filed like biomedical, agriculture, digital video compression, wireless networks. In this paper we present a parallel-pipelined architecture for lifting based two dimensional DWT. We have used lifting based wavelet filter for image compression. Overall area has been reduced by eliminating line buffer and frame buffer from the design. By proper scheduling of the intermediate results this architecture avoid the need of transposition buffer. The architecture has a very small latency (a few cycles) and provide high throughput. By removing redundancy the hardware utilization efficiency has been maximized. The architecture is simulated on ISE simulator and hardware implemented on Artex board.

A fine-grain load-adaptive algorithm of the 2D discrete wavelet transform for multithreaded architectures

The Discrete Wavelet Transform (DWT) is a signal processing technique popularised by its results in data compression. Considerable work has been done in designing novel architectures to perform the DWT, including a systolic architecture designed by the authors, but little attention has been given to the inverse DWT which is needed in applications such as data compression for signal reconstruction. Despite the fact that the inverse DWT is computationally the reverse of the DWT, the hardware design for the architecture is not simply mirrored. Existing designs expect the architecture for the inverse DWT to be a simple follow-on step from the DWT design, however this is not the case. We present one such problem here, showing the FIFO buffering required on the input of the inverse architecture. We show how the size of this buffer can be calculated and compare it to a fixed data array implementation. This work is based on our systolic array design and is an integral part of the inverse DWT design we are working on for image and video compression.

-- Digital watermarking plays a critical role in ensuring the protection, authenticity, and integrity of multimedia content, particularly in today's data-driven environment. In this paper, we present a solution for the watermarking of grayscale images utilizing the Discrete Wavelet Transform (DWT) technique. Our approach focuses on embedding watermark information into the frequency components of the image to achieve a balance between imperceptibility and robustness against common signal processing attacks. A complete software-based implementation of the watermark embedding and extraction process has been developed and evaluated using standard grayscale images. Additionally, we propose a high-level VLSI architecture for real-time implementation of the DWT-based watermarking system, emphasizing efficient resource utilization, parallelism, and low power design. Extensive simulations demonstrate the effectiveness of the DWT-based watermarking method, achieving strong imperceptibility and resilience. This research contributes to the growing field of digital image security by presenting a practical approach to scalable hardware design and opens new directions for future real-time, hardware-accelerated watermarking applications. Key Words: Digital watermarking, Discrete Wavelet Transform (DWT), Grayscale images, VLSI architecture, Image security, Frequency domain, Robustness, Imperceptibility, Hardware design, Real-time systems.

This paper presents an efficient hardware implementation of a hybrid architecture to compute three 8-point transforms - the Discrete Cosine Transform, the Discrete Fourier Transform, and the Discrete Wavelet Transform on a single FPGA. The architecture is based on an element-wise matrix factorization and row-permutation algorithm, where the forward basis transformation matrices are decomposed into multiple sub-matrices and the common units are shared among them. The hardware implementation is parallel, pipelined and multiplication-free; it costs only 2,073 logic cells, 1,476 registers and runs at maximum frequency of 118 MHz with a very high process throughput of 944 Megabits/sec when synthesized onto an Altera FPGA device. The synthesized results for other FPGA technologies are also presented for performance assessment.

Since the discrete wavelet transform (DWT) is a kind of multi-rate transform, it is difficult to design an optimal computation-time architecture for the DWT. In this paper, we propose a highly efficient VLSI architecture for the 1-D DWT decomposition. This architecture contains two stages of systolic decimation filter banks to guarantee a high throughput and an optimal computation time. Using this architecture, N-point samples with J resolution levels can be computed in N clock cycles spending only JL registers, where L denotes filter length. Due to its regular structure, this architecture can be easily scaled up with the tap size of the filters and the number of octaves. The performance of the proposed architecture will be verified by the successful implementation of a 4-tap 3-octave DWT VLSI chip.

The Discrete Cosine Transform (DCT) is largely used for image and video compression in standards like JPEG and MPEG2. Its simplicity coupled with the fact that it can be computed faster than the Discrete Wavelet Transform (DWT) makes it an attractive option for image and video compression. Consequently a lot of research is in progress to determine novel architectures and algorithms for faster DCT computation having high throughput so that it can even be used for real time applications. For example, when transmitting and receiving videos, which have been compressed using MPEG2, one would like to receive the video, without any buffering delay. In other words, one requires such an architecture, which provides the DCTQ coeffecients at a consistent rate, with very low latency between two coeffecients. As such, a highly parallel and pipelined architecture employing 57 pipeline stages and using fast multipliers and adders is proposed in this work. The proposed DCT Processor is implemented in Spartan 3E FPGA.

In this paper, a high-efficient lined-based architecture for the 9/7 discrete wavelet transform (DWT) based on lifting scheme is proposed. The proposed parallel and pipelined architecture consists of a horizontal filter (HF) and a vertical filter (VF). The critical path of the proposed architecture is reduced. Filter coefficients of the biorthogonal 9/7 wavelet low-pass filter are quantized before implementation in the high-speed computation hardware. In the proposed architecture, all multiplications are performed using less shifts and additions. The proposed architecture is 100% hardware utilization and ultra low-power. The architecture has regular structure, simple control flow, high throughput and high scalability. Thus, it is very suitable for new-generation image compression systems, such as JPEG-2000.