Concurrent Viterbi Algorithm With Trace-Back

The Fast Fourier transform (FFT) is a bandwidth-limited algorithm. To alleviate the bandwidth requirement, shared memory is commonly used to accommodate intermediate data. However, given the limited capacity of shared memory in state-of-art GPUs, the intensive shared-memory usage of FFT reduces the number of thread blocks/workgroups that can run concurrently on a streaming multiprocessor/compute unit. In this work, we present our solution, called shared-memory multiplexing, to make more effective use of shared memory. Shared-memory multiplexing is built on a key observation that allocated shared memory is not utilized throughput the lifetime of a thread block/workgroup. We propose our pure software approaches to enable multiple thread blocks to time-multiplex shared memory so as to increase the number of concurrent thread blocks/workgroups on each streaming multiprocessor/compute unit. The improved thread-level parallelism introduces significant performance gains for FFT. On an NVIDIA GTX 480 GPU, our FFT kernel outperforms the NVIDIA library CUFFT V4.0 by 21 % for a 1 k-point FFT with a batch size of 2,048. On an NVIDIA Tesla K20c GPU, our FFT kernel outperforms the NVIDIA library CUFFT V5.0 by 58 % for the same inputs.

Convolutional code is a coding scheme used in communication systems including deep space communications and wireless communications.It provides an alternative approach to block codes for transmission over a noisy channel.The block codes can be applied only for the block of data.The Convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.Viterbi decoder employed in digital wireless communication plays a rife role in the overall power consumption of trellis coded modulation decoder.Power reduction in Viterbi decoder could be achieved by reducing the number of states.A pre-computation architecture with T-algorithm was implemented for this purpose, and when we compare this result with full Trellis Viterbi decoder, this approach significantly reduces power consumption without degrading decoding speed.Convolutional encoding with viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by Additive White Gaussian Noise (AWGN).It operates on data stream and has memory that uses previous bits to encode.The Viterbi Algorithm (VA) is proposed, used for decoding a bit stream that has been encoded using FEC code.The Convolutional encoder adds redundancy to a continuous stream of input data by using a linear shift register.A pre-computation architecture with Viterbi algorithm is implemented for this purpose, Viterbi (Convolutional) encoder and Viterbi decoder are designed and implemented using FPGA technology, which are the essential blocks in digital communication systems.It is particularly suited to a channel in which the transmitted signal is corrupted mainly by AWGN.The Viterbi decoder of Constraint length 7 and code rate ½ is considered.The design is implemented using verilog on Xilinx Spartan 3E and advanced Spartan 6 board and the results and Comparisons are presented.

The Viterbi algorithm is widely adopted in digital communication systems because of its capability of realizing maximum-likelihood signal sequence detection. However, implementation of the Viterbi algorithm requires instantaneous channel state information (CSI) to be available at the receiver. This is difficult to satisfy in some emerging communication systems such as molecular communications, underwater optical communications, etc, where the underlying channel models are highly complex or completely unknown. ViterbiNet, developed in the prior literature, is a promising framework to cope with this challenge, where deep learning (DL) techniques are combined with the Viterbi Algorithm to enable near-optimal signal detection without CSI. This paper offers a non-trivial variation of ViterbiNet based on generative adversarial networks (GAN). Specifically, a novel architecture using GAN is designed to directly learn the channel transition probability (CTP) from receiver observations, which is the only part of the Viterbi algorithm that is channel-dependent. With the learned CTP, the classical Viterbi algorithm can be implemented without modifications. To make the proposed architecture applicable to time-varying channels, we further develop two methods to fine-tune the learned CTP online. In the first method, pilots within each frame are exploited to update the CTP learning network; In the second method, a decision-directed approach is devised to generate training data in real-time, which is utilized to re-train the learning network. By combining these two approaches, the receiver is able to track the dynamic channel conditions without being trained from scratch. Numerical simulations demonstrate the superiority of the proposed design compared to existing methods.

On the performance of distributed objects

In this paper we propose a method for suppressing discrete disturbers in data communication systems where the modulation scheme is implemented using the FFT (Fast Fourier Transform) algorithm. Similar to radio frequency interference (RFI) cancelation in the frequency domain, the compensation is performed after the FFT in the receiver. As opposed to the RFI methods it is not necessary to reserve some of the subchannels for the compensation purpose. However, the new method requires at least one reference tone and all discrete disturbers impairing the data transmission performance must be related to it. For example, this is the case for harmonics where the fundamental acts as reference tone. A detailed derivation of the compensation method is presented and illustrated by means of an example.

The Fast Fourier Transform (FFT) is an important algorithm used in the field of Digital Signal Processing and Communication Systems. The FFT has applications in a wide variety of areas, such as linear filtering, correlation, and spectrum analysis, among many others. This paper describes the development of decimation-in-time radix-2 FFT algorithm with 16 and 32 points. VHDL was used as a description language, and ISE Design Suite as an Integrated Development Environment (IDE).

In many digital signal processing (DSP) applications and communication systems, the main component is the fast Fourier transform (FFT) processing. A characteristic of sinusoids is that they are orthogonal at distinct frequencies whether they are complex or real at any amplitude and phase. All that matters are that the frequencies be different. This property of sinusoid will be implemented to propose a new approach to design and implement fast Fourier transform (FFT) using Radix-42 algorithm, and also how the multidimensional index mapping reduces the complexity of FFT computation will be proposed and discussed in an easy understanding manner. Using mathematical analysis on Radix-4 DFT (discrete Fourier transform) kernel, the formal Radix-4 butterfly structure can be remodeled. This will make the design perspective so simple to implement the mathematical algorithm into the hardware realization model.

In this paper, we concern with designing and implementing a convolutional encoder and Viterbi decoder which are the essential block in digital communication systems using FPGA technology. Convolutional coding is a coding scheme used in communication systems including deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a noisy channel. The block codes can be applied only for the block of data. The convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.The motivation of this paper is to realize a Viterbi decoder having Constraint length 9 and code rate 1/2 by Xilinx 12.4i tools.

System-on-a-chip (SoC) is now a trend in digital design because it gives a lot of advantages over discrete electronic based product such as higher speed, lower power consumption, smaller size, lower cost etc. Reconfigurable platforms such as FPGA, CPLD, and PLD are now being used for designing and implementing SoC due to their low cost, high capacity and tremendous speed. In this project single chip Orthogonal Frequency Division Multiplexing (OFDM) transmitter and receiver have been designed using Verilog HDL. OFDM is a multi carrier modulation technique used in the various digital communication systems like 3G GSM, WiMAX and LTE etc. The main advantage of this transmission technique is its robustness to channel fading in wireless communication environment. There are many applications of OFDM in communication such as digital audio broadcasting, Asynchronous Digital Subscriber Line (ADSL) and High bit-rate Digital Subscriber Line (HDSL) systems. In OFDM, two algorithms digital signal processing algorithm Fast Fourier transform (FFT) and Inverse Fast Fourier Transform (IFFT) are mainly involved. The 8-point IFFT/FFT Decimation-In-Frequency (DIF) with radix-2 algorithm has been analyzed and incorporated in the design. The design has been simulated on the FPGA platform with Altera's Quartus II simulator. Simulation results show that each of the modules of the proposed OFDM is working as desired. The test output achieved from the simulation result of the OFDM has been verified with that of the MATLAB output.

In order to increase the capacity and to suppress co-channel interference in digital communication systems such as mobile cellular and mobile satellite communication systems, the employment of array beamforming techniques has been proposed. However, conventional beamforming methods are not suitable for such cases since these methods were mainly developed for signal detection and direction-of-arrival (DOA) estimation in radar and sonar. In this paper, utilizing the cyclostationary properties of communication signals, we propose three blind cyclic adaptive beamforming (CAB) algorithms and their fast implementation schemes. Several numerical examples are included. These results demonstrate that the CAB algorithms are good candidates for spatial reuse of frequency spectrum in digital mobile communication systems of the next generation.

Fast Fourier transform (FFT) algorithms for single instruction multiple data (SIMD) machines are developed which simultaneously solve any combination of FFTs of different sizes and even different spatial dimensionalities. The only restrictions are that all the periods must be powers of two and that the initial data must satisfy some alignment requirements with the address space in the computer. The degree of parallelism is equal to the sum of the sizes of all the subproblems and the (parallel) solution time is proportional to $\log _2 (m)$, where m is the number of points in the largest subsystem. It is shown that the task of unscrambling the data can be both executed and scheduled efficiently in parallel. Finally, implementations on the MasPar computer are described. The codes can be quickly and easily employed in solving complicated problems, and the interface for the routines may therefore be interesting for sequential FFT codes as well.

The algorithm determines whether or not the punctured state diagram contains a zero-weight cycle. The punctured encoder is assumed to be obtained from a rate 1/b, b<or=n, antipodal encoder of a given constraint length. The algorithm is much simpler to implement in software than the previously known method of calculating the GCD of the determinants of the n distinct (n-1)*(n-1) submatrices of the generator matrix. The computational complexity of the algorithm is no worse than the computational complexity of the GCD method for relatively short constraint lengths, that is, the constraint lengths for which the Viterbi algorithm is implemented.<<ETX>>

Increasing the speed of the wireless communication requires a reliable solution for data transfer. The signal to noise ratio (SNR) of the channel in digital wireless communication is one of the major limitations on the operating performance. To enhance the performance, solution in terms of coded data and error-correcting code has been introduced. Viterbi decoder is one of the techniques used for this purpose and Viterbi algorithm is used for decoding. This algorithm is an extremely fast and efficient method of decoding the coded data from the channel. In this paper, the structure of baseband processing unit and implementation of convolutional encoder and Viterbi decoder is described. The convolutional encoder of rate 1/2 and constraint length 3 and Viterbi decoder of rate 1/2 and constraint length 3 using a TMS320C54 DSP chip is designed.

The key technical elements in designing digital mobile satellite communication systems are identified, and tradeoff studies on the transmission parameters of the satellite link, which were based on experience with an experimental system and the results of field trials, on digital maritime and aeronautical satellite communication systems, are described. The future evolution of the various new communication services to be offered in the digital mobile communication systems are discussed. In the digital mobile satellite communication systems which will be operated under the condition of low C/N and with a signal-level fluctuation due to multipath fading etc., it has been found that the most important requirement is to establish the frame synchronization quickly and maintain it stably in addition to the stable carrier/clock tracking, under this severe link condition. >

Digital communication is a kind of method that carrier is applied to digital signal for transmitting message, or uses digital signal to carry on digital modulation to the carrier and transmits the communication mode. Digital signals such as telegraph, digital data, and analog signals such as voice and image that have been digitally processed can be transmitted. Besides, since the rapid development of modern technology such as computer technology, digital storage technology, digital switching technology and digital processing technology, many signals at equipment and terminal interface are digital signals, hence it is convenient to connect it with the digital communication system. Anyway, the purpose of this project is to use MATLAB programming to construct a digital communication system, demonstrates the results of its operation and analysis eleven different factors may affect the communication of the system. All the functions of different sections are separated and named in their own file with its annotation. The comparisons of results that are influenced by different factors are well explained through figures or tables. All the efforts are targeted to minimize the error between input file and output file to build a qualified digital communication system and prove more useful data for the reference of this field.