Constructing lower and upper bounded delay routing trees using linear programming

A method, based upon a theorem which states that if the optimal solution to a linear programming problem (LPP) without bounds violates one of the upper bound costraints xj≽ uj j=l, …, n for one j only, j=p, say, then in the optimal solution fa the bounded variable linear program we have xp=uD, is proposed. The method introduces one upper bound constraint at a time and would be suitable for the problems where the linear programming (LP) solution violates only a few upper bound constraints.

Low Power and area Efficient Clock Circuit Design

Data aggregation plays an important role in energy constrained wireless sensor networks (WSN). Redundant data can be aggregated at intermediate nodes of a WSN reducing the number of messages exchanged and consequently reducing communication costs. In this work we consider the problem of constructing a dynamic and scalable structure for data aggregation in WSN. Although there are many proposed solutions to data aggregation in WSN, most of them build the data aggregation structure based on the order in which events occur. This kind of structure leads to low quality routing trees and does not address the load balancing problem, since the same tree is used throughout the network life. To tackle these challenges we propose a novel routing protocol called Dynamic and Scalable Tree (DST), which reduces the number of messages necessary to set up a routing tree, maximizes the number of overlapping routes, and selects routes with the highest aggregation rate. The routing tree created by DST does not depend on the order of events and is not held fixed along the occurrence of events. DST was extensively compared with two solutions reported in the literature regarding communication costs, aggregation rate and quality of the routing tree. Results show that the routing tree built by DST provides the best aggregation quality compared with other algorithms outperforming them for different scenarios in all evaluations performed.

Clock skew resulted by process variation becomes more and more serious as technology shrinks. In 2010, ISPD held a high performance clock network synthesis contest; it considered supply-voltage variation and wire manufacturing variation. Previous works show that the main issue of variation induced skew is on supply-voltage variation. To trade off power and supply-voltage variation induced skew more effectively, we adapt a tree topology which use a timing model independent symmetrical tree at top level to drive the bottom level non-symmetry trees. Our method gives top tree more power budget to reduce supply-voltage variation induced skew and greedily saves power consuming in bottom level. Experimental results are evaluated from the benchmarks of ISPD contest 2010. Compared with state-of-the-art cross link work, the proposed technique reduces 10% of power consumption on average and also improves the run time.

Since the size of on-chip memory greatly affects the chip cost, sensors targeting at tiny size and low cost cannot afford large memory module. The process of efficiently routing the packets in networks containing memory constraint nodes is an interesting and challenging research topic. In this paper, we propose an integrated routing protocol for large-scale sensor networks consisting of both memory-constraint nodes and memory-sufficient nodes. In our design, a spanning-tree is first built to ensure that every node pair is connected through a tree route. Source nodes can directly use tree routes to deliver short or urgent messages; they can also choose to discover shortcuts through a reactive routing process. Intermediate nodes, depending on their memory conditions, either create routing entries to guide data forwarding, or simply relay all packets following tree routes. Simulations verify the feasibility of our protocol and show it a promising scheme empowering highly flexible network designs.

Terrain mobility performance optimization: Fundamentals for autonomous vehicle applications. Part I. New mobility indices: Optimization and analysis

Renewable energy sources particularly solar energy have a great potential in fulfilling the energy demand in far-off rural areas where providing electricity is difficult from the existing transmission line network of the main grid. Photovoltaic (PV) sources possess stochastic nature either operating standalone or connected to the main power grid. The standalone systems have various issues like voltage fluctuations and power quality which also have an adverse effect on equipment utilizing the power generated from PV sources. Standalone PV systems consist of PV panels, a storage system, and a charge control unit (CCU). To fully utilize the energy generated from PV panels all these components as well as loads must be optimized to provide an efficient operating scenario in microgrids. Required operating condition is achieved by a distributed optimization method with the lower and upper bound constraints in terms of population dynamics of microgrid components. To implement this, a microgrid is considered with 10 Standalone PV systems with residential loads. The analysis shows how power converges to a reference value and provides a stable voltage profile for the standalone microgrid systems in rural areas.

This paper investigates the interference alignment solution for a fully connected (1 × 1, 1/2) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">K</sup> K-user symmetric interference network with K single-antenna relays. The criterion of minimum total interference plus noise leakage (Min-INL) is considered with a set of lower and upper bound power constraints at each relay. And an iterative algorithm is proposed to alternatively optimize the precoders at transmitters, decoders at receivers and relay beamforming weights. There have closed-form solutions for subproblems to solve precoders and decoders. Subproblem with variables of relay beamforming weights is formulated as nonconvex quadratically constrained quadratic programs (QCQP) and efficiently solved by semi-definite relaxation (SDR). Simulation results demonstrate that the criterion of Min-INL with proposed algorithm obtains higher throughputs than that of minimum total interference leakage (Min-IL) and the conventional orthogonal transmission scheme.

Welcome to the 11th ACM/IEEE International Symposium on Low Power Electronics and Design!.The 2006 edition of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) welcomes you to the beautiful, on-the-lake setting of the Tegernsee area in Germany, within a one hour drive from Munich. On a par with this great location, a strong and diverse technical program features two keynote talks from leaders in the field, a technical panel, four embedded tutorials, and, new for this year, three half-day tutorials scheduled for the last day of the symposium.Dr. Christoph Kutter, Senior VP Products and Systems, Infineon Technologies, will give a keynote on design challenges for mobile communication devices. The Thursday keynote is given by Barry Dennington, Senior Vice President, NXP Semiconductors/CTO/SoC Design Technology, who will present an industrial view on the demands of a convergent communications, consumer and automotive market, the technology challenges a semiconductor company faces and the solutions that lead to actual products with a few examples. The Friday panel is titled "Flexibility and Low Power; a Contradiction in Terms?". Moderated by Peter Wintermayr, Editor in Chief of Markt and Technik, panelists Reiner Hartenstein, Univ. Kaiserslautern; Heinrich Meyr, RWTH Aachen Univ. and Chief Scientific Officer CoWare; and Steve Leibson, Tensilica, will discuss whether configurable or re-configurable computing offer solutions for low power design.The four embedded tutorials during the first two days of the conference are organized around two major themes: (1) low power circuit design and technologies; and (2) low power systems and energy management. Two embedded tutorials on sub-threshold design and variability/low power design from experts from MIT, University of Michigan, and IBM Research are paired with two others on energy harvesting for battery limited systems and low power portable applications from researchers from NEC Labs and University of California. New for this year, ISLPED will offer three half-day tutorials on hot topics such as leakage aware design, micropower analog design, and addressing fault-tolerance/variability and power issues from system to circuit levels. The tutorials feature presenters from OFFIS, Intel, University of North Carolina, Carnegie Mellon University, and IBM Research.Out of 214 submissions received in early March, only 75 strong technical papers were accepted for presentation in paper or poster sessions, yielding an acceptance rate of 26% for regular and short papers (56 papers), or 35% including 19 posters. Topics range from low power analog and RF design, power aware circuit design and tools, and architecture techniques for low power, to system and application level power management. The program is organized in twelve technical sessions featuring long (30 min) and short (20 min) paper presentations, as well as two interactive poster sessions that will provide an additional venue for authors and symposium attendees to interact in an informal setting. Following the tradition of ISLPED, this year's event also includes exhibits featuring tools and methodologies from leading vendors of low power or power-aware design tools. New for this year, the program includes an industry session that will highlight contributions showcased by companies participating in the ISLPED exhibits. Winning entries to the annual Low Power Design Contest will also be featured in a separate technical session.

102.4 GS/s Impulse Sampling Circuit with Low Power and Low Timing Error Clock Generation

Welcome to the 11th ACM/IEEE International Symposium on Low Power Electronics and Design!.The 2006 edition of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) welcomes you to the beautiful, on-the-lake setting of the Tegernsee area in Germany, within a one hour drive from Munich. On a par with this great location, a strong and diverse technical program features two keynote talks from leaders in the field, a technical panel, four embedded tutorials, and, new for this year, three half-day tutorials scheduled for the last day of the symposium.Dr. Christoph Kutter, Senior VP Products and Systems, Infineon Technologies, will give a keynote on design challenges for mobile communication devices. The Thursday keynote is given by Barry Dennington, Senior Vice President, NXP Semiconductors/CTO/SoC Design Technology, who will present an industrial view on the demands of a convergent communications, consumer and automotive market, the technology challenges a semiconductor company faces and the solutions that lead to actual products with a few examples. The Friday panel is titled Flexibility and Low Power; a Contradiction in Terms?. Moderated by Peter Wintermayr, Editor in Chief of Markt and Technik, panelists Reiner Hartenstein, Univ. Kaiserslautern; Heinrich Meyr, RWTH Aachen Univ. and Chief Scientific Officer CoWare; and Steve Leibson, Tensilica, will discuss whether configurable or re-configurable computing offer solutions for low power design.The four embedded tutorials during the first two days of the conference are organized around two major themes: (1) low power circuit design and technologies; and (2) low power systems and energy management. Two embedded tutorials on sub-threshold design and variability/low power design from experts from MIT, University of Michigan, and IBM Research are paired with two others on energy harvesting for battery limited systems and low power portable applications from researchers from NEC Labs and University of California. New for this year, ISLPED will offer three half-day tutorials on hot topics such as leakage aware design, micropower analog design, and addressing fault-tolerance/variability and power issues from system to circuit levels. The tutorials feature presenters from OFFIS, Intel, University of North Carolina, Carnegie Mellon University, and IBM Research.Out of 214 submissions received in early March, only 75 strong technical papers were accepted for presentation in paper or poster sessions, yielding an acceptance rate of 26% for regular and short papers (56 papers), or 35% including 19 posters. Topics range from low power analog and RF design, power aware circuit design and tools, and architecture techniques for low power, to system and application level power management. The program is organized in twelve technical sessions featuring long (30 min) and short (20 min) paper presentations, as well as two interactive poster sessions that will provide an additional venue for authors and symposium attendees to interact in an informal setting. Following the tradition of ISLPED, this year's event also includes exhibits featuring tools and methodologies from leading vendors of low power or power-aware design tools. New for this year, the program includes an industry session that will highlight contributions showcased by companies participating in the ISLPED exhibits. Winning entries to the annual Low Power Design Contest will also be featured in a separate technical session.

ZigBee is the emerging industrial standard for ad hoc networks based on IEEE 802.15.4. Due to characteristics such as low data rate, low price, and low power consumption, ZigBee is expected to be used in wireless sensor networks for remote monitoring, home control, and industrial automation. Since one of the most important goals is to reduce the installation and running cost, ZigBee stack is embedded in small and cheap micro-controller units. Since tree routing does not require any routing tables to send the packet to the destination, it can be used in ZigBee end devices that have limited resources. However, tree routing has the problem that the packets follow the tree topology to the destination even if the destination is located nearby. We propose the shortcut tree routing protocol to reduce the routing cost of ZigBee tree routing by using the neighbor table that is originally defined in the ZigBee standard. While following the ZigBee tree routing algorithm, we suggest forwarding the packet to the neighbor node if it can reduce the routing cost to the destination. Simulation results show that the shortcut tree routing algorithm saves more than 30 percent of the hop count compared with ZigBee tree routing.

A 3.4713-approximation algorithm for the capacitated multicast tree routing problem

Clock networks account for a significant fraction of the power dissipation of a chip and are critical to the performance. This paper presents theory and algorithms for building a low power clock tree. Two low power schemes are used: a reduced swing scheme and one using multiple supply voltages. We analyze the issue of tree construction and present conclusions relevant to various technology generations according to the National Technology Roadmap of Semiconductors (NTRS). Our experimental results show that the power could be saved an average of 45% for a 0.25 /spl mu/m technology using multiple supply voltages, and 31% using reduced swing buffers.

This paper proposes a unified flow for functional verification using assertion-based and coverage-based verification techniques. For each technique, both simulation and formal methodologies are combined together in order to accelerate the coverage closure and achieve the functional verification goal. The assertion-based and coverage-based verification techniques are well defined individually. However, our aim is to approach the combination of these techniques beside low power verification and clock domain crossing verification techniques in one complete verification flow. This approach will lead to a clear and unified verification methodology which can be the guideline for building an efficient functional verification environment.