Constructing runtime models of complex software-intensive systems for analysis of failure mechanism

Maintenance of embedded software systems is faced with multiple challenges, including the exploration and analysis of the actual system's runtime behavior. As a fundamental technique, tracing can be used to capture data about runtime behavior as a whole, and represents one of the few methods to observe and record data about embedded systems within their production environments. In this paper we present a software-based, function-boundary tracing approach for embedded software systems. It uses static binary instrumentation, which implies only lightweight memory and performance overheads. To further reduce these overheads, instrumentation can be configured per trace, i.e., activated only for a specified group of functions without having to recompile the system. The technique can be characterized by its robust implementation and its versatile usage. It is complemented by a visualization framework that allows for analysis and exploration of a system's runtime behavior, e.g., to examine thread interaction. To show the technique's applicability, we conclude with a case study that has been applied to an industrial embedded software system.

In nano scale, the degradation failure mechanism for CMOS device such as hot-carrier injection, breakdown of thin oxides, electro-migration and NBTI (Negative Bias Temperature Instability) induced damage become a major reliability concern. Physics-of-Failure method is used in lifetime prediction of nano scale CMOS, which integrates loading condition, package, geometry and material with time-to-failure. Common lifetime models for these mechanisms are described and a method to estimate lifetime of nano-scale CMOS device, with simulation based on Physics-of-Failure. Through Failure Mode, Mechanism and Effect Analysis, failure mechanism and lifetime models are clarified and selected, as well as structure, material, processing parameters and environment conditions. Stress analysis, which includes electrical stress by EDA and thermal analysis by FEA (Finite Element Analysis) are carried out to acquire parameters in lifetime model. Damage accumulation algorism and competing theory are utilized to predict lifetime of the device. This method will help CMOS device design engineers better understand the failure mechanisms in nano-scale and take design-for-reliability measures.

The selection of test points is one of the key steps for electronic systems on prognostic and health management (PHM). Parameters of reasonable test points can characterize the fault features of electronic systems and provide effective input information for diagnosis and prognosis. In this chapter, an improved method of test point selection for analog electronic systems on diagnosis and prognosis is proposed and a case study is presented. The proposed method includes several steps: (1) fault risk analysis: determine susceptibility areas for the electronic system based on environmental stresses analysis and life analysis; (2) functional simulation analysis: based on the circuit schematic diagram, establish the functional simulation model for the system and list all accessible nodes, then identify the relationship between nodes and faults by using correlation models; (3) fault simulation analysis: Combine with the previous analysis of failure modes and mechanisms and set corresponding faults in the functional simulation software; (4) Comprehensive evaluation and selection: evaluate fault simulation data of each test point, and select appropriate test points for the system. The presented method has the following features: considering the specific product condition and failure mechanisms, focusing on high-risk mechanisms, and basing on fault simulation to revise testability model to make it closer to the real fault situations.KeywordsTest point selectionDiagnosisPrognosticSimulationAnalog electronic systems

This paper presents a comprehensive analysis of the short-circuit failure mechanisms in commercial 1.2 kV planar silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) under 400 and 800 V bus voltage conditions. The study compares two products with varying short-circuit tolerances, scrutinizing their external characteristics and intrinsic factors that influence their short-circuit endurance. Experimental and numerical analyses reveal that at 400 V, the differential thermal expansion between the source metal and the dielectric leads to cracking, which in turn facilitates the infiltration of liquid metal and results in a gate–source short circuit. At 800 V, the failure mechanism is markedly different, attributed to the thermal carrier effect leading to the degradation of the gate oxide, which impedes the device's capacity to switch off, thereby triggering thermal runaway. The paper proposes strategies to augment the short-circuit robustness of SiC MOSFETs at both voltage levels, with the objective of fortifying the device's resistance to such failures.

Fatigue behavior of CFRP/Al adhesive joints — Failure mechanisms study using digital image correlation (DIC) technique

Field failure mechanism study of solder interconnection for crystalline silicon photovoltaic module

Precisely elucidating the influence of various orientations on the fracture performance of unidirectional fiber‐reinforced composites (UD FRCs) is crucial for evaluating the structural integrity of defect UD FRCs. Existing studies lack in‐depth analysis of failure mechanisms and accurate prediction of fracture toughness for different orientations. Quasi‐static eccentrically‐loaded single edge crack tension (ESET) fracture tests were conducted in air on compression‐molded unidirectional T300 carbon fiber/7901 epoxy composites with fiber orientations spanning 0°–90° (15° increments). The digital image correlation technology was used to reveal the deformation and failure mechanisms during the fracture process. Then, the mixed‐mode I‐II trilinear cohesive zone model (CZM) was developed and used to predict fracture behavior under different orientations. It was found that increasing the orientation angle leads to a higher initiation fracture toughness, consistent with the observed trend in maximum tensile strain ε yy . The relationship between fracture toughness and ε yy has been established. Moreover, combined with microanalysis, it can be observed that as the orientation angle increases, the failure mechanism shifts from fiber–matrix interface debonding, matrix cracking, and fiber bridging to matrix shear failure, fiber breakage, and pull‐out. Finally, the CZM method combined with the established B‐K parameters relationship can quickly and accurately predict fracture toughness under any orientations, and the maximum error is less than 3%. The current research on the damage mechanism and reliability evaluation of FRCs is of great significance.

Being one of the basic features of Internetware, self-adaptation means that the software system can monitor its runtime state and behavior and adjust them when necessary according to pre-defined policies. Focusing on the three fundamental issues of self-adaptation, including the scope, operability and trustworthiness, a software architecture (SA) centric approach for Internetware’s self-adaptation is presented in this chapter. All of the self-adaptive actions, i.e. monitoring, analyzing, planning and executing, are performed based on SA. In detail, runtime state and behavior of Internetware are represented and changed in the form of runtime soft-ware architecture. The knowledge for self-adaptation is captured, organized and reasoned in the form of SA so that automatic analysis and decision-making are achieved.

Recently, more attention is paid to the researches and practices on how to use software architecture in software maintenance and evolution to reduce their complexity and cost. The key in such architecture-based maintenance and evolution is to recover software architecture from existing systems. Almost all studies on architecture recovery focus on analyzing the source code and other documents. Such recovered software architecture can hardly capture runtime states and behaviors of the system. At the same time, current work pays little attention on how to change the system directly via manipulating the recovered software architecture. This paper presents a novel approach to recovering software architecture from component based systems at runtime and changing the runtime systems via manipulating the recovered software architecture. Containing much more details than the designed software architecture, the recovered software architecture can accurately and thoroughly describe the actual states and behaviors of the runtime system. It can be described formally with the extension of traditional architecture description language, which enables the recovered software architecture to absorb the semantics embedded in the designed software architecture. The recovered software architecture can be represented as multiple views so as to help different users to control the complexity from different concerns. Based on the reflective ability of the component framework, the recovered software architecture is up-to-date at any time and changes made on it will immediately lead to the corresponding changes in the runtime system. The approach presented in this paper is demonstrated on PKUAS, a reflective J2EE (Java 2 Platform Enterprise Edition) application server, and the performance is also evaluated.

This paper considers the problem of runtime system deviations from requirements specifications. Such deviations may arise from lack of anticipation of possible behaviors of environment agents at specification time, or from evolving conditions in this environment. We discuss an architecture and a development process for monitoring system requirements at runtime to reconcile the requirements and the system's runtime behavior.This process is deployed on three scenarios of requirements-execution reconciliation for the Meeting Scheduler system. The work builds on our previous work on goal-driven requirements engineering and on runtime requirements monitoring.

An integrated real-time tool set is described that consists of a schedulability analyzer and a real-time monitor/debugger for the ARTS kernel, which is being built for a distributed real-time testbed. The schedulability analyzer, called Scheduler 1-2-3, is an X11 window-based interactive tool and can verify whether the given real-time tasks can meet their deadlines under a specific scheduling policy. An advanced real-time monitor, ARM, also runs on the X11 window and visualizes the target system's runtime behavior in real time. ARM can be used with Scheduler 1-2-3 to analyze simulated runs and its monitorability. >

Unidirectional transmission mechanism (UTM) is widely used in mechanical field. The UTM studied in this paper is the core component of the aircraft hatch system, which is used to transfer the power of the motor to drive the hatch to be retracted and locked automatically after the motor closes. Aiming at the failure mode exposed in the experiment, the matching relations of both geometric parameters and mechanical parameters are studied, and the force analysis model of the UTM is established. The results show that the load of the UTM reaches its maximum at 65°, and if the friction coefficient between the friction plates is less than its critical value, braking failure will occur, which is in agreement with the test phenomena. In order to further verify the failure mechanism and obtain the effects of the gradual damage on the performance, a parameterized simulation model is established, through which failure phenomenon in the test is recovered, and the correctness of the failure mechanism analysis is verified. Finally, combined with its failure mechanism, the maintenance advice is proposed, and the validity is verified through the simulation model.

With the inherent advantages of material, SiC MOSFET is promising in many applications. There is much research on failure analysis of SiC MOSFET under extreme conditions. A comprehensive review is critical to provide reference for weak locations of chip in device design or application stage. Under three types of extreme conditions of high temperature, high frequency and irradiation, the failure mechanism and mode, characterization, withstand capability and factors affecting reliability are reviewed in detail. The analysis of failure mechanism can provide a basis for chip designers to improve chip performance for specific operating conditions, and provide device users with advice on circuit design. A clear safe working area allows practitioners to maximize the performance of the device. The methods to improve reliability of SiC MOSFET are proposed at the end of the paper.KeywordsExtreme conditionsSiC MOSFETReliability

Failure mechanism analysis under compression loading of unidirectional carbon/epoxy composites using micromechanical modelling

In order to meet the harsh working environment and complex and changeable stress conditions, the low-temperature and high-pressure liquid carbon dioxide conveying system used in oil extraction will choose metal bellows for transportation. In this paper, the bellows in an accident section are investigated and observed by the working environment and characterization methods such as macroscopic analysis, metallographic analysis, EDS component analysis, fracture scanning electron microscopy analysis, and related mechanical performance test methods. The failure mechanism of the accident is preliminarily judged, and the unidirectional fluid–structure coupling model and the standard k-ω turbulence model are used as the calculation models for subsequent simulation. Combined with Fluent finite element simulation analysis, it is verified that the failure is caused by a welding defect, the maximum stress of the metal bellows under normal conditions is less than its own yield strength, and the material can work normally. When the welding crack is greater than 2 mm, the strength of the workpiece weld will be reduced, and the stress concentration has exceeded the yield strength that the workpiece can bear, causing failure fracture at the welding defect part. Combined with ANSYS simulation of accident defects, compared with bellows without defects, the stress at the crack will increase with the increase in the inlet flow velocity and decrease with the increase in temperature, and the flow rate will have a greater influence on it. Therefore, in actual working conditions, the stiffness and fatigue life of the conveying system can be improved by appropriately reducing the liquid flow rate and increasing the temperature. It provides a reference for the future application research of bellows and the research on bellows fracture failure.