Continuous-Time Approach to Discrete-Time PID Control for UPS Inverters - A Case Study

It is common practice to measure the instantaneous load current for realizing current trajectory control for UPS inverters. A recent paper describes an interesting sliding control mode scheme for 1-ph inverters with an LC filter in which the A.C. load current needs to be monitored. A modification to the scheme is presented in this paper which enables sliding mode control by monitoring the instantaneous D.C. line current and the load voltage. A simple observer can estimate the load current. The use of the observer helps in overcoming the problem of high voltage swings experienced by current sensors and errors due to common mode signals.

This paper presents a novel synchronous-frame repetitive controller for three-phase UPS inverters. Distinguished from conventional repetitive control techniques, the proposed synchronous-frame approach minimizes the repetitive control time delay to one-sixth of the fundamental period such that the dynamic response is significantly improved. In order to overcome the harmonic distortions under severe load conditions (e.g., unbalanced and nonlinear), in this paper, three synchronous rotating frames are deliberately selected, in each of which the repetitive controller is incorporated. Resultantly, the (6n ±1)th harmonics as well as the triplen harmonics are compensated. Moreover, a high-performance fourth-order linear phase infinite-impulse-response filter is applied to further enhance the accuracy of steady-state tracking. The proposed controller is programmed on the 16-bit fixed-point digital signal processor (TI TMS320LF2407) and eliminates high-resolution current sensors for cost effectiveness. Simulations and experimental tests have been carried out based on an 18-kW three-phase UPS system. Low total harmonic distortion (<;0025;) has been achieved under heavily distorted nonlinear load and unbalanced load. Fast dynamic response has been demonstrated during step load transients.

Sequences having the minimum peak aperiodic autocorrelation sidelobe level one (1) are called Barker Sequences. Such sequences have been used in numerous real-world applications such as channel estimation, radar and spread spectrum communication etc. Unfortunately, the longest known biphase and quadriphase Barker sequences are of lengths 13 and 15 respectively. In this paper Modified Simulated Annealing Algorithm (MSAA) is used to design thirty-two phase sequences, which have good autocorrelation properties. Some of the synthesized results are presented here. The properties of the sequences up to length 24 have Barker properties which were not reported in literature earlier. The sequences of lengths from 4 to 289 have autocorrelation properties better than Frank codes. The synthesized 32-phase sequence sets are promising for practical application to radar and spread spectrum communication systems.

A robust PWM power amplifier whose transient response characteristics do not deteriorate against an extensive load change and/or direct-current power-supply voltage change is needed. In this paper, a method for designing a digital robust controller for PWM power amplifier which can satisfy such demands is proposed. First, a nominal model of PWM power amplifier is derived from the linear approximation. The controlled object is described by discrete-time systems with consideration of the input dead time. It is shown that a digital controller can be designed in almost the same way as the previously proposed analog controller and then 2-degree-of-freedom digital robust systems are constituted. An integral-type control system is built by carrying out an equivalent conversion. The LC filter and the digital controller which satisfy the design specifications are determined by the proposed design procedure. Especially, the sampling period of the digital controller is determined suitably. A DSP is used to realize the digital controller obtained here. An experiment demonstrates that the proposed digital controller can satisfy all the specifications.

This paper presents a frequency‐dependent droop scheme for paralleling UPS inverters with no control interconnection, so the inverters can be tightly connected with the load. At the fundamental frequency, the reference voltage of the inverter is generated as a reactor connected between the inverter and the load. The intention is to control the real and reactive power sharing of inverters with the Q‐V and P‐ω droop scheme employed in the power system without needing a true transfer reactor. At the harmonic frequency, the reference voltage is generated as a resistor connected between the inverter and the load. The intention is that the load harmonic current can be shared equally and the voltage waveform distortion will be low. Two 1KVA single‐phase inverters are designed and implemented, some simulation and experimental results are provided for demonstrating the effectiveness of the proposed approach.

This study introduces an innovative disturbance observer to tackle external disturbances and model uncertainties, along with a control strategy based on Lyapunov functions, ensuring global asymptotic stability for a single-phase multilevel inverter for UPS applications. The stability analysis of the proposed method is presented, based on two theorems. The first Theorem guarantees presents a disturbance observer, provides a bounded estimation error for the unknown disturbance, in the single-phase UPS inverter (UPSI). The bounded estimation is then used in designing an observer-based robust controller in the second Theorem, which ensures the convergence of tracking error to a small neighborhood of the origin. The numerical and practical results indicate that the developed control scheme ensures global stability and leads to the desired sinusoidal voltage with an almost low THD. Meanwhile, almost zero steady-state error in the output voltage (OV), and robust dynamic performance under uncertainties and disturbances are attained.

A digital control algorithm for the three-phase sinusoidal voltage inverter with an output LC filter has been developed. To take the transient of the LC filter during the discretization time into consideration, a fourth-order matrix state equation of the current and the voltage on the d-q frame is discretized. Precise discrete equations for the inverter are introduced. Using these equations, a deadbeat controller consisting of a d-g current minor loop and a d-q voltage major loop, with precise decoupling of the d-q components, was developed. The voltage major loop controller assures the sinusoidal output voltage and stabilizes the system. A deadbeat controller is used because both the current minor loop and the voltage major loop can used one sampling response. The validity of these techniques is confirmed by simulation studies. This method is expected to be useful for direct digital control of large-capacity sinusoidal voltage inverters using low-switching-frequency devices.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this paper, a combined current limiting algorithm is proposed for voltage controlled inverters. The proposed method combines the analog and digital current limiting algorithms. It provides fast response and better voltage waveform quality even during the transient stages. The proposed system is implemented and tested with a three-phase 10kVA UPS inverter. In addition, both digital and analog current limiting techniques are also implemented and tested for the same conditions and the obtained results are compared with the proposed combined current limiting algorithm. It is seen that proposed hybrid algorithm provides successful current limiting performance with its fast response in short circuit and overcurrent conditions, and significantly improves the reliability and fault tolerance of the inverter.

This paper highlights the problems encountered when attempting to supply a high crest factor load from a UPS inverter. Inverter voltage control using an inner loop consisting of an average current mode controller and an outer loop is investigated. The choice of parameters, filter components and compensators, are discussed. Simulation results show the steady state and dynamic performance of the inverter. The addition of load current feedforward can cause the system to become unstable and is explained with the aid of simplified control models. The inverter under consideration is rated at 30 kVA with a PWM switching frequency of 15 kHz.

A novel control method of a three-phase PWM inverter with LC filter is proposed. The transfer function of LC filter is the same as that of 2nd order low pass filter(2nd LPF) which has a zero damping ratio. A simple method of implementing 2nd LPF with damping ratio is to add resistor to inductor or capacitor of LC filter. In an industrial application, it is not practical to adopt damping resistor because it results in losses being proportional to square of current flowing through resistor. Instead of using damping resistors, the proposed active damping control(ADC) utilizes all pass filter(APF) and considers inherent processing delay of digital controller. The overall transfer function of the proposed method is the same as a 2nd LPF and its damping ratio is also controllable via control variables. Detailed design and implementation of controller is also presented. Experiments are conducted with a 7.5kVA induction motor drive system controlled by PWM converter and inverter. Test waveforms are also presented to verify the proposed LC filter control algorithm.

In this study, an extended Lyapunov-function-based control strategy that assures global asymptotic stability is proposed for single-phase UPS inverters. The Lyapunov function is formed from the energy stored in the inductor and capacitor due to the fact that the system states converge to the equilibrium point if the total energy is continuously dissipated. It is shown analytically that the classical Lyapunov-function-based control leads to a globally asymptotically stable system at the expense of steady-state errors in the output voltage, which exist due to the lack of outer voltage loop in the control input. Therefore, an extended Lyapunov-function-based control strategy is proposed, which eliminates the steady-state error without destroying the global stability of the closed-loop system. The steady state and dynamic performance of the proposed control strategy has been tested by simulations and experiments under resistive and diode bridge rectifier loads. The results obtained from a 1-kW inverter demonstrate that the developed control strategy not only offers global stability, but also leads to good quality sinusoidal voltage with a reasonably low THD, almost zero steady-state error in the output voltage, and fast dynamic response under linear and nonlinear loads.

Dual active bridge (DAB) converters have been gaining increasing popularity in the context of high-frequency solid state transformers. However, modeling of a DAB converter remains a challenge to retain the ripple information for the design of high performance stable digital control under uniform sampling. This paper proposes a discrete-time framework using approximate discrete-time models considering various practical parasitics. These models are used to derive various discrete-time small-signal transfer functions under phase shift modulation using both voltage mode and current mode control techniques. The accuracy of the proposed models is verified through SIMPLIS simulation as well as experimentation in time-domain and in the frequency domain using SIMPLIS simulation. Finally, a design case-study using digital voltage-mode control is considered for a prototype DAB converter under phase-shift modulation with a power rating of 50 W and switching frequency of 500 kHz. The digital controller is implemented using an FPGA device, and the test results are demonstrated. The proposed framework can be extended to different modulation techniques as well as other isolated DC-DC converter topologies to design high frequency digital control.

This paper presents a method correlating the design of power circuits and controllers. The design of power circuits considers the voltage regulating performance as well as the attainable duty cycle of the inverter during the dynamic response. The voltage regulating performance make the design of power circuits have to consider many parameters that reveals the inherent capability of the inverter. The attainable duty cycle provides a way for evaluating the effectiveness of the controller related to the inherent capability of the inverter. A dual loops inductor current control technique is adopted as an example for the control of inverter in this paper. Through the introduction of a phase lead compensator in the current loop, the digital controller design can be simplified as an analog controller design such that the analysis is intuitive and the performance can be quantified easily. A multiple mode control technique is presented to enhance the performance of the voltage controller to achieve a more effective capability utilization of the inverter. The voltage THD (total harmonic distortion) at high crest factor (CK) load can be reduced significantly. A 2 kVA system is designed and implemented. The effectiveness of the proposed method is confirmed with some simulation and experimental results.

Interactive digital control using PMBus protocol can significantly improve performance, efficiency and reliability in high frequency low voltage DC (LVDC) microgrid applications using online optimization through shared clock and data. Modeling and analysis of digitally controlled standalone DC-DC converters, considering finite sampling delays, have been well reported in the past; however, modeling and analysis of fast scale stability and performance limits, under finite sampling delay and clock shift, have not been investigated so far in digitally controlled LVDC microgrids. This paper considers an intermediate bus architecture (IBA), consisting of an intermediate bus converter (IBC) followed by a point-of-load (PoL) converter, under clock-synchronized digital current mode control (DCMC). Considering the IBA dynamics, a discrete-time (DT) framework is proposed, and DT small-signal models are derived for stability and performance analysis. It is shown that the clock shift between individual converters and the sampling delays of their corresponding digital controllers have significant impacts on the fast-scale stability of the overall IBA system, which may lead to severe fast-scale instability with complex nonlinear phenomena and resulting in much higher (inductor) current ripple and RMS quantities. Simulation case studies are presented, and the stability boundaries are found to be consistent with the analytical predictions. The proposed framework will be helpful to design stable digital control in DC microgrids.

Real-time programming has always been one of the most challenging programming disciplines. Real-time programming requires comprehensive command of sequential programming, concurrency, and, of course, time. Real-time programming has many application domains. In this chapter, however, we structure our discussion around digital control systems for the following two reasons. Firstly, digital control systems represent a large portion of real-time software in a diverse set of industries. Examples include automotive power train control systems, aircraft flight control systems, electrical drive systems in paper mills, or process control systems in power plants and refineries. Many of these systems distribute their components over networks with significant communication delays. Therefore, we also discuss networked real-time programming (Section 7). The second reason is pedagogical. Digital control is defined by a set of abstractions that are real-time programmable and mathematically tractable in the context of the dynamics of physio-chemical processes. The abstractions clearly define what application engineers (control engineers) expect of real-time programming. These abstractions therefore constitute a precise definition of the real-time programming problem (Section 2). Control engineers design in difference equations and often use modeling tools such as Simulink to simulate and validate their control models. The part of Simulink most commonly used to specify digital control, i.e., discrete-time with the discrete fixed-step solver and mode:auto, is well-explained by the so-called synchronous semantics [7, 38]. The key abstraction, we call the synchronous abstraction, is that any computation and component interaction happens instantaneously in zero time or with a delay that is exactly the same at each invocation. For example, if a controller computes every 20 msec, either the controller is assumed to read its inputs, compute its control, and write the corresponding outputs instantaneously at the beginning of each period in zero time, or to read its inputs instantaneously at the beginning of the period, compute during the period, and write the corresponding output exactly 20 msec (one period) later. In control parlance, these are the causal and strictly causal cases, respectively. Systems of difference equations can directly be expressed and structured in this model. The inclusion of strictly causal components (components with delays of a period or more) is typically required to break feedback loops and to account for the unavoidable computation or communication delays that will be present in the real control system. Real-time programmers design in interrupt handlers, device drivers, and schedulers, which are concepts on levels of abstraction that are obviously unrelated to difference equations. The result is a conceptual and technical disconnect between control model and real-time code that bedevils many control building projects. The control engineer specifies a Simulink design the real-time programmer finds unimplementable. The realtime programmer then fills in gaps to produce an implementation the control engineer finds uncontrollable. The process of interaction as the two iterate to produce a correct design is prolonged by the different backgrounds of control engineers and real-time programmers. This gap explains many of today’s problems in real-time software design for digital control such as high validation and maintainance overhead as well as limited potential for reusability and scalability.