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  • https://doi.org/10.1109/eidwt.2013.28Copy DOI Icon

Cost Evaluation of Three-Dimensional Network-on-Chip

  • Sep 1, 2013
  • Ji Wu +3 more
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Abstract

The convergence of three-dimensional (3D) technology and network-on-chip(NoC), the so-called 3D NoC, bring out new architectures and higher performance than traditional 2D NoCs. However, cost is always the dominant factor of adoption of a new technology. In order to evaluate the economic feasibility of volume production of different architectures of 3D NoCs, we compare the fabrication costs of four 3D NoC architectures: 3D mesh, 3D stacked mesh, ciliated mesh and separated mesh, and analyze the variation of costs of different designs with increasing number of processing cores. Conclusion is drawn that when the number of gates is relatively small, 3D mesh and 3D stacked mesh are recommendable, however, when the number of gates is large, 3D mesh and ciliated mesh are cost-efficient than 3D stacked mesh and separated mesh. To the author's knowledge, this is the first disquisition on costs of different architectures of 3D NoCs. It provides economic reference to designing 3D NoCs for volume production in the future.

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