Countering Power Analysis Attacks UsingReliable and Aggressive Designs

Cryptographic devices are vulnerable to the nowadays well known side channel leakage analysis. Secret data can be revealed by power analysis attacks such as Simple Power Analysis (SPA), Differential Power Analysis (DPA) and Correlation Power Analysis (CPA). First, we give an overview of DPA in mono-bit and multi-bit cases. Next, the existing multi-bit DPA methods are generalized into the proposed Partitioning Power Analysis (PPA) method. Finally, we focus on the CPA technique, showing that this attack is a case of PPA with special coefficients and a normalization factor. We also propose a method that allows us to improve the performance of CPA by restricting the normalization factor.Keywordsside channelpower analysisDPAmulti-bit DPAPPACPAcorrelationDESAES

SUMMARY Recently, side-channel attacks have become a serious problem. These attacks estimate the secret keys of cryptography circuits embedded in hardware. In particular, the most threatening side-channel attacks are differential power analysis and correlation power analysis, which use the correlation between information processing and power consumption, which are related to secret keys in cryptography circuits. Therefore, new measures are required to prevent confidential information in cryptography circuits from being leaked to side-channel information, such as power consumption. When designing preventive measures, resistance to side-channel attacks, for instance tamper resistance, must be evaluated. This study proposes a new simulation method by which tamper resistance can be verified in the algorithm and architecture design phases. Experimental results show the validity of the proposed simulation method. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 186(2): 40–51, 2014; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.22342

Encryption chips are specialized integrated circuits that incorporate encryption algorithms for data encryption and decryption, ensuring data confidentiality and security. In China, the domestic SM4 algorithm is commonly utilized, as opposed to the international AES encryption algorithm. These widely implemented encryption standards have been proven to be difficult to crack through crypt analysis methods Currently, power consumption side-channel attacks are the most prevalent method. They involve capturing power consumption data during the encryption process and subsequently recovering the encryption key from this data. The two leading methods are Differential Power Analysis (DPA) and machine learning techniques. DPA does not necessitate prior knowledge but relies heavily on the number of power consumption curves. With only 50 power consumption data points, the accuracy is a mere 80%. Machine learning methods require prior knowledge, achieving an accuracy rate above 95% with only 30 power traces, albeit with training times typically exceeding 15 min. In this paper, a distributed energy analysis attack approach was presented based on Correlation Power Analysis (CPA). The power consumption data was divided into 16 subsets, with each subset corresponding to 8 bytes of the key. By training each subset separately, the 8-byte key’s corresponding power consumption data is reduced to only 100 dimensions, resulting in a 76% decrease in cracking time and a 3% improvement in cracking accuracy rate.This article also trains a more complex 256 classification model to directly crack the final key, achieving a success rate of 28% in cracking 128-bit passwords with only 1 power trace

Security in embedded systems is of critical importance since most of our secure transactions are currently made via credit cards or mobile phones. Power analysis-based side channel attacks have been proved as the most successful attacks on embedded systems to retrieve secret keys, allowing impersonation and theft. State-of-the-art solutions for such attacks on public key cryptographic algorithms, such as elliptic curve cryptography, mostly in software, hinder performance and repeatedly attacked using improved techniques. To protect these public key ciphers from both simple power analysis and differential power analysis, as a hardware solution, we propose to take advantage of the inherent parallelisation capability in multi-modulo residue number systems (RNS) architectures to obfuscate the secure information. Random selection of moduli is proposed to randomly choose the moduli sets for each key bit operation. This solution allows us to prevent power analysis, although still providing all the benefits of RNS. In this study, the authors show that differential power analysis, cross correlation analysis and correlation power analysis for a simple binary double-and-add operation are thwarted using their solution.

Random delays and dynamic frequency switching are widely adopted in smartcards and embedded systems as temporal hiding countermeasures to side channel attack.Temporal hiding is regarded as efficient to enhance the security of cryptographic devices. However, spectral analysis with Fast Fourier Transform is a powerful method to defeat temporal hiding countermeasures. Spectral analysis shares the same merit with integration different power attack. Multi-bit spectral analysis is enhanced with partitioning power analysis, which is much more effective than the correlation power analysis in the spectral domain. Multi-bit spectral analysis effectively defeats temporal hiding countermeasure with floating-mean dynamic frequency switching countermeasure. It is suggested cryptographic devices should employ other countermeasures together with hiding to ensure side channel security.

PRESENT, proposed by A. Bogdanov et al. in CHES 2007, is an ultra-lightweight symmetric cipher for extremely constrained environments such as RFID tags and sensor networks. In this article, a representative platform, 0.25 µm 1.8 V standard cell circuit is proposed to complement the PRESENT, the simulation-based ASIC experimental environment is built to acquire power data. According to the fact that the power consumption of a digital circuit implemented in the CMOS technology depends on the data that the circuit is processing, we create the hypothetical circuit model for differential power analysis (DPA) against the special block cipher, PRESENT. Two Different statistical methods, multi-bit DPA and correlation power analysis (CPA), are conducted in this paper to analyze the power data sampled from the power traces. We can attack all secret key bits after first two rounds DPA attack. Our results present the vulnerability to power analysis attack against the hardware implementations of PRESENT.

Cryptography is securing information using mathematical techniques like encryption and decryption. Cryptanalysis uses side-channel attacks to undermine security. The efficient type of power analysis of the side channel and Differential Power Analysis (DPA) statistically assesses the power use of the cryptographic method and provides private details. This paper proposes the design of a Compact PRESENT S-box (CPSB), using Three-Phase Dual Rail Pre-Charge Logic (TDPL) combined with Charge Balancing Symmetric Pre-Resolve Adiabatic Logic (CBSPAL). The primary contribution of this research lies in the development of a power-efficient logic style that improves the performance of the S-box while maintaining conflict against DPA attacks. By employing TDPL, the design achieves consistent power consumption across various input configurations, thereby mitigating the risk of side-channel attacks. The focus of this work is to propose an innovative implementation approach rather than the security aspects of cryptography itself. The proposed methodology proves a substantial reduction in power overhead and area, making it suitable for resource-constrained environments, like Internet of Things (IoT) applications. A correlation study is carried out to calculate the Compact Present S-box implementation's DPA resistance characteristic. The power traces are examined. The proposed design makes power consumption consistent and decreases area and power overhead by 15.3% and 13.6%, respectively. Performance indicators for the security are NED, NSD, and Pearson correlation coefficient. The connection is the same for all conceivable input and key pairings. When compared with other designs, the NED and NSD were determined to be 0.02% and 0.01%, respectively.

Cryptographic systems can potentially suffer from various attacks which are a consequence of vulnearability of side channel information to analysis attacks. The nature of digital circuits is prone to electromagnetic and power analysis (EMA and PA) attacks. Interconnects in cryptographic circuits emanate information through electromagnetic signals which can be exploited using EMA. Complementary Metal Oxide Semiconductor (CMOS) circuits are vulnearable to leak of computational information through leakage and dynamic power consumption. Dynamic power consumption of cryptographic engines is a rich source to sink in the data under process. The hardware implementation of cryptographic algorithms undermine the security of encrypted system against non brute-force-attacks. The attackers collect and analyse the leakage information of cryptographic circuits to detect the secrete key. The parameters sensitivity of the device and circuits make the cryptographic engines vulnearable to fault injection and inherent inconsistency of the circuits. Dynamic and static power comprise two major components of power consumption of digital circuits. Both power components vary with data under process. This exhibits power consumption has data dependency in digital circuits. To make noisy power profile, various countermeasures have been proposed against Differential Power Analysis (DPA) attacks. In this research, false glitch cells is proposed to work as a countermeasure to generate random transitions and power spikes to scramble power profile. The mathematical foundation of security implications of false glitch cells against Correlation Power Analysis (CPA) attacks is investigated. Moreoever, the security efficiency of utilizing false glitch cells is verified with different metrics.

International audience

Side-channel attacks (SCAs) are powerful attacks that could be used to retrieve keys from electronic devices. Several physical leakage sources can be exploited in SCAs, such as power, time, heat, and so on. Heat is one of the side-channels that is not frequently analyzed by attackers in the literature due to the high noise associated with thermal traces. This article investigates the practicality of adapting power-based SCAs [i.e., correlation power analysis (CPA) and deep-learning-based power attacks (DL-based PA)] for thermal attacks and refer to them as correlation thermal attack (CTA) and DL-based thermal attack (DL-based TA). In addition, we introduce a new attack called progressive CTA (PCTA). We evaluate the different thermal SCAs against an unprotected and protected software implementation of Rivest–Shamir–Adleman (RSA). Our results show the practicality of the three attacks (i.e. CTA, DL-based TA, and PCTA) as a 100% key recovery is realized.

The additional information (side effects) in Elliptic Curve Cryptography (ECC) hardware can be used to attack cryptographic systems. Additional information related to time, power consumption and electromagnetic radiation. Side channel attacks have been done with SPA (Simple Power Analysis), DPA (Differential Power Analysis), SEMA (Simple Electromagnetic Analysis) and DEMA (Differential Electromagnetic Analysis). Some scalar multiplication algorithm can be used to countermeasure SPA attack on elliptic curve cryptography. In this study, conducted experiments side-channel attacks ECC hardware implementations use binary algorithms by observing power consumption of ECC processor on FPGA. Experimental of side-channel attack is conducted to guess the secret key for data encryption and decryption by looking at the physical differences on hardware side effects. In this study, side-channel attack experimental is successful 100% get the key by analyzing of power consumption ECC processor.

Since the vulnerability of cryptosystems to differential power analysis (DPA) was reported in 1999, various power analysis attacks and corresponding countermeasures have been studied. With the scaling down of supply voltage and CMOS technology below 90 nm, leakage power plays an increasing role in the overall power dissipation. Future cryptosystems need to address this trend, though it has not been of concern yet in low- cost cryptosystems such as smartcards and RFED tags which currently use older technologies and low performance transistors. In this paper, we explore the impact of leakage power on conventional DPA and the feasibility of a novel leakage-based DPA (LDPA). We first use SPICE simulations to explore the leakage dependence on input patterns of logic gates implemented in 90 nm, 65 nm, and 45 nm CMOS technologies. Then we simulate a successful LDPA on a subset of a DES cryptosystem with only 120 rounds, in contrast to the 200 rounds reported for a conventional DPA in 180 nm technology. Furthermore, we demonstrate how even a DES implementation using a DPA-resistant logic style can be broken with LDPA in 2000 rounds, compared with the conventional DPA using more than 5000 rounds.

The chosen-message method is used to be employed in conducting Simple Power Analysis (SPA) attack by means of selecting special input messages. However, it is difficult to make distinction by visual observation i.e., SPA in practical IoT hardware environment. In this paper, we proposed a practical chosen-message correlation power analysis (CPA) attack which combines the chosen-message method with CPA for side channel attack. Then, we adopt other two practical chosen-messages, 1 and n + 1, to attack Boscher’s right-to-left binary exponentiation algorithm which is wildly considered as an efficient side channel resistant algorithm. Finally, this paper presents a countermeasure to resist the chosen-message CPA attack over Boscher’s algorithm without nullifying its countermeasure features to Differential Power Analysis (DPA) and Differential Fault Analysis (DFA). To validate the proposed attack method and countermeasure, a 1024-bit RSA coprocessor is constructed on the Xilinx Virtex-5 with the Side-channel Attack Standard Evaluation Board (SASEBO) to implement Boscher’s algorithm as well as our proposed algorithm and launched the proposed attack on it separately. The experiment results show that the proposed attack and countermeasure are feasible and efficient.

In current countermeasure design trends against differential power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate arrays (FPGA) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on FPGA. This article describes our novel masked dual-rail pre-charged memory approach, called “intra-masking dual-rail memory (IMDRM) on LUT”, and its implementation on FPGA for Side-Channel Attack-resistant (SCA-resistant) AES. In the proposed design, all unsafe nodes, such as unmasking and masking, and parts of dual-rail memory with unsafe buses (buses that are not masked) are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. Inputs and outputs of all LUTs are masked, and so can be considered safe signals. Several LUTs can be combined to create a safe SBox. The design is independent of the cryptographic algorithm, and hence, it can be applied to available cryptographic standards such as DES or AES as well as future standards. It requires no special placement or route constraints in its implementation. A correlation power analysis (CPA) attack on 1,000,000 traces of AES implementation on FPGA showed that the secret information is well protected against first-order side-channel attacks. Even though the number of LUTs used for memory in this implementation is seven times greater than that of the conventional unprotected single-rail memory table-lookup AES and three times greater than the implementation based on a composite field, it requires a smaller number of LUTs than all other advanced SCA-resistant implementations such as the wave dynamic differential logic, masked dual-rail pre-charge logic, and threshold.

Differential power analysis (DPA) has been shown to be an effective attack on cryptographic systems capable of releaving secret data by measuring power consumption. DPA resistant circuits currently experience severe problems in terms of performance, area, and power. Although different countermeasures to reduce DPA attacks have been proposed and implemented in general, such protections do not make attacks infeasible. Additionally, most are dual rail logic families, Delay Based Dual Rail Precharge Logic (DDPL) with high resistance is presented and significantly lower overheads in performance, area, and power than other DPA resistant logic styles. The Delay Based Dual Rail Precharge Logic (DDPL) shows a certain improvement in Normalized Energy Deviation(NED) with respect to other dual rail logics.