Counting spanning trees using modular decomposition

Algorithmic aspects of switch cographs

A fully dynamic algorithm for modular decomposition and recognition of cographs

Counting trees in a graph is #P-complete

Fully dynamic representations of interval graphs

Floating-point arithmetic is ever-present in computer systems. All most all computer languages has supports a floating-point number types. Most of the computer compilers called upon floating-point algorithms from time to time for execution of the floating-point arithmetic operations and every operating system must be react virtually for floating-point exceptions like underflow and overflow. The double-precision floating arithmetic is mainly used in the digital signal processing (filters, FFTs) applications, numerical applications and scientic applications. The double-precision floating arithmetic operations are the addition, the subtraction, the multiplication, and the division. Among the all arithmetic operations, multiplication is widely used and most complex arithmetic operation. The double-precision (64-bit) floating point number is divide into three fields, Sign field, Exponent field and Mantissa field. The most significant bit of the number is a sign field and it is a 1-bit length, next 11-bits represents the exponent field of the number and remaining 52-bits are represents the mantissa field of the number. The double-precision floating-point multiplier requires a large 52×52 mantissa multiplications. The performance of the double-precision floating number multiplication mainly depends on the area and speed. The proposed work presents a novel approach to decrease this huge multiplication of mantissa. The Urdhva Tiryagbhyam technique permits to using a smaller number of multiplication hardware compared to the conventional method. In traditional method adding of the partial products are separately done and it takes more time in comparison with the proposed method. In proposed method the partial products are concurrently added with the multiplication operaton and it can reduce the time delay. The double-precision floating multiplier is implemented using Verilog HDL with Xilinx ISE tools on Virtex-5 FPGA.

Decoding of real BCH DFT (RBDFT) codes is considered in this paper. RBDFT codes find applications in several areas. Though the generator matrix of RBDFT codes is real, the parity check matrix is still complex, because of which complex arithmetic operations are necessary at the decoder. But for a real message vector, the syndromes of RBDFT code preserve Hermitian symmetry. This Hermitian symmetric structure is exploited and a new alternative subspace based formulation is proposed in this paper. The performance of the proposed formulation is identical to the current state-of-art RBDFT decoding algorithm, while it requires only real arithmetic operations. Simulation results are provided which demonstrates the reduction in the decoding complexity with no degradation in the performance.

In this paper, we study undirected multiple graphs of any natural multiplicity $$k > 1$$ . There are edges of three types: ordinary edges, multiple edges and multi-edges. Each edge of the last two types is a union of $$k$$ linked edges, which connect 2 or $$k + 1$$ vertices, correspondingly. The linked edges should be used simultaneously. If a vertex is incident to a multiple edge, it can be also incident to other multiple edges, and it can be the common ending vertex to $$k$$ linked edges of a multi-edge. If a vertex is the common end of some multi-edge, it cannot be the common end of any other multi-edge. Special attention is paid to the class of divisible multiple graphs. The main peculiarity of them is a possibility to divide the graph into $$k$$ parts, which are adjusted on the linked edges and which have no common edges. Each part is an ordinary graph. The definition of a multiple tree is stated and the basic properties of such trees are studied. Unlike ordinary trees, the number of edges in a multiple tree is not fixed. In the article, the estimation of the minimum and maximum number of edges in the divisible tree is stated and proved. Next, the definitions of the spanning tree and the complete spanning tree of a multiple graph are given. The criterion of completeness of the spanning tree is proved for divisible graphs. It is also proved that a complete spanning tree exists in any divisible graph. If the multiple graph is weighted, the minimum spanning tree problem and the minimum complete spanning tree problem can be set. In the article, we suggest a heuristic algorithm for the minimum complete spanning tree problem for a divisible graph.

On CD-chromatic number and its lower bound in some classes of graphs

The Maximum Weight Stable Set (MWS) Problem is one of the fundamental algorithmic problems in graphs. It is NP-complete in general, and it has polynomial time solutions on many particular graph classes, some of them defined by forbidden subgraphs. A classical example is the result of Minty that the MWS problem is polynomially solvable for the class of claw-free graphs. The complexity of the MWS problem is unknown for the class of P5-free graphs. We give a survey on recently obtained efficient algorithms for the MWS problem for several graph classes defined by forbidden subgraphs where the algorithm avoids to recognize whether the (arbitrary) input graph is in the class i.e. the output is either a correct solution of the MWS problem or the fact that the input graph is not in the class. Such algorithms were called robust by Spinrad. The algorithms use the concepts of modular decomposition and of clique width of graphs.

Consider a class of graphs $$\mathcal{G}$$ having a polynomial time algorithm computing the set of all minimal separators for every graph in $$\mathcal{G}$$ . We show that there is a polynomial time algorithm for treewidth and minimum fill-in, respectively, when restricted to the class $$\mathcal{G}$$ . Many interesting classes of intersection graphs have a polynomial time algorithm computing all minimal separators, like permutation graphs, circle graphs, circular arc graphs, distance hereditary graphs, chordal bipartite graphs etc. Our result generalizes earlier results for the treewidth and minimum fill-in for several of these classes. We also consider the related problems pathwidth and interval completion when restricted to some special graph classes.

Chebyshev polynomials and spanning tree formulas for circulant and related graphs

In this thesis we study the number of spanning trees in some classes of graphs. This is made possible by the famous matrix tree theorem established by Kirchhoff in 1847 which states that the number of spanning trees in a finite graph is given by the product of the non-zero eigenvalues of the combinatorial Laplacian of the graph divided by the number of vertices. We adapt techniques derived by Chinta, Jorgenson and Karlsson in 2010 for d-dimensional discrete tori to circulant graphs with first generator equals to 1 and to d-dimensional degenerating discrete tori. They are degenerating in the sense that d-p sides of the tori are tending to infinity at the same rate while the p other sides tend to infinity sublinearly with respect to the d-p sides. Furthermore, the results on d-dimensional discrete tori enable to derive asymptotics for the number of spanning trees on d-dimensional orthotope square lattices. Other results obtained in this thesis concern closed formulas for the number of spanning trees in directed and non-directed circulant graphs where the generators vary, that is, they linearly depend on the number of vertices.

Now a day's various real time applications and image processing applications requires hardware that can perform various complex arithmetic operations. These operations can be performed by using binary logarithmic number system. This paper includes binary logarithmic circuit based on FPGA. Above architecture uses combinational logic circuit elements and fixed point data path number format. The architecture is able to calculate the logarithm of integer number, fractional number and integer fractional number. This architecture is designed in Xilinx Virtex-5 device. This architecture consumes minimal FPGA resources that are shown by device utilization summary. Finally error analysis is done which shows that architecture has minimal number of errors considering fractional number and fixed point numbers.

The paper presents algorithms for the generation of Residue Number System (RNS) triples with $SQ=2^{k}-1$ and quadruples with $SQ=2^{k}$ for some k. Triples and quadruples allow us to design efficient hardware implementations of non-modular operations in RNS such as division, sign detection, comparison of numbers, reverse conversion with using of a diagonal function from requiring division with the remainder by the diagonal module SQ. Division with a remainder in the general case is the most complex arithmetic operation in computer technology. However, the consideration of special cases can significantly simplify this operation and increase the efficiency of hardware implementation. We show that there are 5573 good RNS triples (2301 even and 2372 odd) with elements less than 10 000, as the values of SQ vary from $2^{5}-1$ to $2^{27}-1$ . In contrast, RNS quadruples with $SQ=2^{k}$ seem to be quite rare. Restricting our search to sums of the elements in a quadruple less than 4000 we find that exactly 31 such quadruples exist. Their values of SQ vary between 220 and 230 with always even exponent. We suggest the measure of RNS balance and find perfectly balanced RNS among triples according to this measure. We demonstrate the advantages of more balanced quadruples by means of hardware implementation.

Digital Signal Processing (DSP) applications are dominated by complex arithmetic operations, which heavily degrade their performance. Targeting to accelerate the execution of Residue Number Systems (RNS)-based DSP applications, in this work, we focus on optimizing the design of the modulo 2n + 1 Add-Multiply (AM) operation with weighted operands. We incorporate in our design a new direct recoding of the modulo 2n + 1 sum of two weighted operands in its Modified Booth form. Compared to the conventional design of first instantiating an adder and then, driving its output to a multiplier, the proposed fused AM design yields considerable delay, area and power gains.