Current testing viability in dynamic CMOS circuits

True single phase clock logic techniques, e.g. with alternating arranged Nand P-logic cells, yield easily to design circuits with standard cells and high speed potential. The disadvantages are a difficult clock tree design and high power consumption. To realize every logic function, dual rail or differential styles are chosen which increase clock load. This paper presents a method to speed up dynamic single clock circuits. The advantage of asynchronous logic is that the critical path delay is the sum of only the evaluation times of the single logic blocks without wasting time for waiting, latches, or redundant logic. Therefore, this work assembles small asynchronous chains of dynamic logic blocks into one period of the global clock to minimize the unused time per clock cycle (AC-TSPC). However, the synchronous single phase clocking scheme is maintained. The advantages of this method are shorter latencies for calculations, power reduction by smaller clock trees and no need for latches, and a simpler clock distribution network due to increased clock skew tolerance. The results of the simulations of an 8/spl times/8 bit multiplier in TSPC and in AC-TSPC show an enhancement in power-reduction of 40% for the logic and of 89% for the clock tree with a latency reduction of 40% and more in comparison with TSPC.

In the previous work, the problem of finding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay, we reduce the number of the LP constraints to be linear in circuit size. For example, the 469-gate c880 circuit requires 3,611 constraints as compared to the 6.95 million constraints needed with the previous method. The reduced constraints provably produce the same exact LP solution as obtained by the exponential set of constraints. For the first time, we are able to optimize all ISCAS'85 benchmarks. For the c7552 circuit, when the input to output delay is constrained not to increase, a design with 366 delay buffers consumes only 34% peak and 38% average power as compared to an unoptimized design. As shown in previous work, the use of delay buffers is essential in this case. The practicality of the design is demonstrated by implementing an optimized 4-bit ALU circuit for which the power consumption was obtained by a circuit-level simulator.

It has been reported (Kuang et al., 1997; Lu et al., 1997) that SOI passgate circuits suffer history effects and adverse initial-cycle parasitic bipolar currents, which cause difficulties in circuit timing and limit direct design reuse from original bulk circuits. SOI device body history can also induce transfer characteristics mismatch in dual-railed static or dynamic CMOS circuits, resulting in speed degradation or functional failures. This paper describes an efficient technique to alleviate initial-cycle bipolar currents while retaining the low-V/sub t/ floating body feature when the SOI devices concerned are on. We also present a dynamic body discharge technique to eliminate the mismatch problems in cross-coupled SOI CMOS topologies, for use in a variety of circuit families such as cascade voltage switch logic, latch-type sense amplifiers and analog operational amplifiers.

If a test set exists for a CMOS circuit which detects all the stuck-open faults in it in the presence of arbitrary circuit delays and timing skews, then the circuit is said to be robustly testable. We saw earlier in Chapter 2 that dynamic CMOS circuits, such as domino CMOS and cascode voltage switch logic circuits, are always robustly testable. However, this is not true for all static CMOS circuits. In this chapter, procedures for designing robustly testable static CMOS circuits will be discussed. Generally, the circuits are designed to be robustly testable with respect to single stuck-open faults. However, we will also discuss a method which guarantees robust testability with respect to multiple faults.KeywordsTest VectorpMOS TransistorCMOS CircuitNAND GateDelay FaultThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This paper presents a method and circuit for correcting faults in logic systems. The method, called feedback (RFB), is similar in some respects to triple modular redundancy (TMR), but has an improved error probability with respect to transient errors. Simulation results indicate an improvement by about two orders of magnitude compared to traditional TMR. CMOS circuits are presented for implementing restorative feedback. For binary logic, a dynamic CMOS circuit is considered. For multiple-valued logic, a semi-floating gate implementation is presented.

In this paper, we show that a single clock phase is sufficient to build several skew safe communication circuits. The communication is guaranteed to function for all types of clock skew. No delay matching is necessary in the clock distribution network and the circuits are skew insensitive for all process, temperature and supply variations. Stage interconnect rules are summarized in a graph, suitable for use in CAD tools for both timing verification and synthesis of extremely timing robust systems.

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. E. I. Boemo, S. López-Buedo, and J. M. Meneses, "Some experiments about wave pipelining on FPGA's", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v. 6, n. 2, p. 232 - 237

PurposeA low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.Design/methodology/approachThis paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.FindingsThe proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.Originality/valueThis work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

Usually, realizing self-timed pipelined data-paths for high performance Digital Signal Processors (DSPs) dynamic CMOS logic is used. In this paper a novel methodology to implement computational elements of self-timed data-paths is presented. It is based on the use of both static and dynamic CMOS modules. The former act as overlapped execution circuits and they anticipate their computation with respect to the dynamic blocks. The above method applied to a 32-bit addition stage allows a performance gain to be obtained of up to about 40% and a reduction in power dissipation of about 33%, with a reasonable area overhead compared to conventional design.

Dynamic threshold MOS circuits can adjust devices' threshold according to the states of the circuits and thus offer higher speed and better saving of energy at low voltage. In this paper a new fast bulk true single phase clocking (TSPC) dynamic threshold MOS scheme for both NMOS and PMOS is introduced. In this scheme the common substrate of the NMOS logic or PMOS logic is dynamically controlled: the potential changes only when these transistors need to work and keeps high threshold when they are shut down. And the scheme uses the charge recovery technique of the substrate, to further reduce power. It is capable of operating at 0.8V or even lower. The proposed scheme is shown to be 33.45% faster and has 20.86% energy savings compared to the regular TSPC logic circuits, during HSPICE simulation

Power and area will remain the main constraints in the designing of VLSI circuits. Dynamic CMOS logic circuits are broadly designed for high performance circuits due to their high speed. Conversely, the demerit of dynamic logic style is its high noise sensitivity and during cascading several problems like charge sharing and charge degradation arises. The main cause of this is the sub-threshold leakage current flowing through the pull down network and with continuous technology scaling, this problem is getting more and more severe. Compared to static CMOS circuits which have larger capacitance and offers more delay, Dynamic circuits are used to improve those parameters of design. In this paper we have proposed a new circuit in order to improve the power consumption by applying a multi-threshold technique. Simulations are done in Cadence for 90nm with IBM technology for OR gates with supply voltage of 1v.

Power dissipation is becoming a prime design constraint in VLSI systems. The new key words for evaluating a design's performance are low power and high speed. This requires an overall system design review that considers suitable algorithms, architectures, circuits, and technology. In synchronous systems, the clocking network sets the frame that contains the whole design. It must be simple and robust. Power consumption in the clock distribution network has usually been a substantial part of the system total power consumption. New true single phase latches and flip flops are presented that are slope-insensitive, fast, and have data dependent power consumption. Flip flops are presented that work between DC and 1.7 GHz clock frequencies in a 1 /spl mu/m CMOS technology. Methods are given that result in power saving in the clock system by reducing the clock rate by half for the same data throughput on the system level.

A programmable dynamic logic circuit for use in reconfigurable fabrics is described. The proposed circuit is based upon dynamic domino CMOS logic. This approach for implementing reconfigurable logic provides added flexibility in programmable datapaths by allowing the implementation of complex logic structures that are not feasible with the configurable logic blocks used in conventional FPGAs. An important application is the acceleration of the critical path found in the carry-chain of a wide-bit adder.

Specific features of supercritical hydrothermal crystallization synthesis (SHCS) by a rapid heating flow type method are reviewed. The attractive features of the method are (i) quantitative production of ultrafine particles, and (u) control of particle morphology or crystal structure by varying the pressure, temperature or reaction atmosphere (reducing or oxidizing). In this study, we use this method to continuously produce LiCoOz fine crystals that are used as for the cathode materials of rechargeable lithium ion batteries. LiOH and Co(NO& were chosen as starting materials. For oxidizing Co(II) to Co(III), O2 was introduced into the reactor after decomposing HzOz aqueous solution in a preheating tubing. LiCoO2 particles were formed in a single phase at supercritical conditions. scanning electron micrographs showed that the particle size was in the range of 500 to 1,000 nm in diameter. Electrochemical characterization was performed by a constant current discharge and charge test. Little decrease in the discharge capacity suggests high stability of the LiCoOz crystals prepared by this method.

Back-to-back capacitive bank switching is the most severe duty among capacitive current switching duties because the amplitude of the inrush current with high frequency is very large. In this paper, 36kV back-to-back capacitive current switching tests of test duty 2(BC2) were carried out with vacuum circuit breaker. And the tests were performed with a series of separate making tests of 120 operations followed by a series of CO tests of 120 operations due to limitations of the test plant according to IEC standards 62271-100. The two types of VCB were tested with single phase and the test results were compared in terms of pre-arcing time, break down voltage distribution, contact surface after tests, contacting area, and field enhancement factor.