DANNA 2

The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to the "design verification crisis ", as it is known among engineers. Today's verification challenges require powerful testbenches and high-performance simulation solutions such as Hardware Simulation Accelerators and Hardware Emulators that have been in use in hardware and electronic system design centers for approximately the last decade. In particular, in order to accelerate functional simulation, hardware emulation is used so as to offload calculation-intensive tasks from the software simulator. However, the communication overhead between the software simulator and hardware emulator is becoming a new critical bottleneck. We tackle this problem by partitioning the code running on the software simulator into two sections: the testbench HDL (hardware description language) code that communicates directly with the design under test (DUT) and the rest C-like testbench code. The former section is transformed into synthesizable code while the latter runs in a general purpose CPU. Our experiments demonstrate that the proposed method reduces the communication overhead by a factor of about 5 compared to a conventional hardware emulated simulation

The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to the verification crisis , as it is known among engineers. Today's verification challenges require powerful testbenches and high-performance simulation solutions such as Hardware Simulation Accelerators and Hardware Emulators that have been in use in hardware and electronic system design centers for approximately the last decade. In particular, in order to accelerate functional simulation, hardware emulation is used so as to offload calculation-intensive tasks from the software simulator. However, the communication overhead between the software simulator and hardware emulator is becoming a new critical bottleneck. We tackle this problem by partitioning the code running on the software simulator into two sections: the testbench HDL (hardware description language) code that communicates directly with the design under test (DUT) and the rest C-like testbench code. The former section is transformed into synthesizable code while the latter runs in a general purpose CPU. Our experiments demonstrate that the proposed method reduces the communication overhead by a factor of about 5 compared to a conventional hardware emulated simulation

In neuromorphic applications, resistive memory solutions (implemented as Resistive Random Access Memory or ReRAM) have significant potential in emulating the desired two-terminal synaptic functionality of real synapses. One of the unique features for the demonstrated ReRAM devices includes conductance modulation, which allows for the implementation of the synaptic weight between neuronal elements. In this paper, we illustrate the multi-resistance level switching capabilities of our unique ReRAM-CMOS hybrid system, which is a demonstration vehicle for implementation of a memristive Dynamic Adaptive Neural Network Array, also known as mrDANNA. Discrete resistance levels have been achieved through application of varying gate voltage and discrete electric pulses in the order of nanoseconds.

A software simulator is developed for verifying the VLBI Correlation Subsystem (VCS) trial product hardware. This software simulator includes the delay tracking, fringe rotation, bit-jump, FFT analysis, re-quantization, and auto/cross-correlation functions so as to confirm the function of the VCS trial product hardware. To verify the effectiveness of the developed software simulator, we carried out experiments using the simulation data which is a mixed signal with white noise and tone signal generated by software. We confirmed that the performance of this software simulator is similar as that of the hardware system. In case of spectral analysis and re-quantization experiment, a serious problem of the VCS hardware, which is not enough for expressing the data stream of FFT results specified in VCS hardware specification, was found by this software simulator. Through the experiments, the performance of software simulator was verified to be efficient. In future, we will improve and modify the function of software simulator to be used as a software correlator of Korea-Japan Joint VLBI Correlator (KJJVC).

A hardware design and software simulation are presented to control and monitoring greenhouse parameters such as: air temperature, humidity provision and irrigation by means of simultaneous ventilation and enrichment. A set of smart wireless sensor modules to control and monitoring system were designed and tested. The heart of the smart sensor is a microcontroller that receives data on greenhouse environment conditions from many sensors installed inside and outside. The smart sensor transfers the data to and from a PC via a wireless transmission system. Accordingly, it changes the state of greenhouse command devices, heaters, fans and vapor injectors to reach the desired condition. A friendly GUI using high level language was developed to carry out the monitoring tasks. The program implements the control algorithms comparing the received data with set points, sending control signals to the smart sensors in order to reach the desired conditions. Performance of the designed system was tested by installing it in the model greenhouse with a set of smart sensors.

Todaypsilas verification challenges require high-performance simulation solutions, such as hardware simulation accelerators and emulators, that have been in use in hardware and electronic system design centers for approximately the last decade. In particular, in order to accelerate functional simulation, hardware emulation is used so as to offload calculation-intensive tasks from the software simulator. However, the communication overhead between the software simulator and the hardware emulator is becoming a new critical bottleneck. In our work we introduce a novel way of repartitioning the simulation between software and hardware in order to minimize this communication bottleneck. Using the techniques described in this paper we are able to offload a big part of the work that is traditionally done by the software simulator, onto the hardware emulator. Our experiments, using real-world designs, demonstrate that the proposed method reduces significantly the communication overhead and outperforms the conventional hardware emulation systems by a factor of more than 7. Finally, we provide a way of observing and modifying the internal state of the hardware emulator while the test is running.

Transfer learning for power system fault location using artificial neural networks

The modeling methods of HEMTs and HBTs using Wiener dynamic neural network (DNN) are reviewed in this paper. The Wiener-type DNN is divided into dynamic part and nonlinear part, which can accurately model various microwave devices. The specific Wiener-type DNN structures of HEMTs and HBTs are explained respectively. The Y-parameters and H-parameters are used for small-signal analysis of HEMTs and HBTs respectively. Examples of modeling GaAs HEMT and InGaP/GaAs HBT using Wiener-type DNN method are shown. Through comparing the experimental results of Wiener-type DNN model, time-delay neural network model and other models of the two sample transistors, it is proved that Wiener-type DNN model has excellent accuracy and convergence performance.

<p indent="0mm">To achieve carbon neutrality in the power system, renewable energies (RENs), such as wind and solar power, are being rapidly installed. However, due to their strong intermittency and high uncertainty, balancing power supply and demand is becoming increasingly difficult. Time-of-use and real-time pricing (RTP) are crucial methods to ensure effective consumption of RENs, encouraging flexible resources on the demand side to work with RENs through demand-side response. Air conditioning loads represent a significant portion of urban loads, with &gt;50% of the peak load in China. They can use the building’s thermal inertia to provide regulation services, a current area of focus for demand-response research. To adapt to the RTP mechanism in the future electricity market, this study explores demand-side optimization control technology for an ice storage system in a large-scale district cooling system (DCS). An optimal control method for an ice storage system is proposed, based on compound second-sampling reinforcement learning (RL), which can effectively manage uncertainties from users’ cooling demands and real-time market prices. First, a Markov decision process (MDP) is constructed to address the operational control issue of the DCS. Second, a model-free RL algorithm is used to solve the MDP. Third, the compound second-sampling mechanism is proposed to improve training efficiency and convergence performance by combining immediate return and temporal-difference error to overcome the issue of low learning efficiency caused by uniform random sampling in the traditional RL algorithm. Finally, the experimental results confirm the effectiveness of the proposed method.

With the rapid development of the Industrial Internet of Things (IIoT) and intelligent manufacturing, massive amounts of heterogeneous and non-independent, identically distributed (non-IID) data are continuously generated in industrial environments. Large models have demonstrated strong generalization and transfer capabilities, offering new possibilities for predictive maintenance, anomaly detection, and intelligent decision-making in IIoT scenarios. However, the deployment of such models in industrial environments faces challenges due to resource constraints in communication and computation. To address this problem, this paper proposes a collaborative optimization framework that integrates client-side feature learning, a hierarchical client–edge–cloud federated aggregation, and network-computing resource scheduling for efficient large-model embedding training. A parameter search method based on the Kepler Optimization Algorithm (PSKOA) is introduced to jointly optimize the three interdependent dimensions: client-side model structure parameter, federated aggregation parameters, and scheduling strategy. Evaluations demonstrate that the proposed method significantly reduces model loss by 41.7% and shortens training time by 13.4% compared to the traditional Genetic Algorithm-based method. Additionally, the proposed method achieves 12.5% lower model loss and 3.1% faster training time compared to the Particle Swarm Optimization-based method. These results highlight that the proposed method effectively enhances both training efficiency and convergence performance by jointly optimizing communication, computation, and model structure, making it a practical and scalable solution for large-model embedding training in resource-constrained IIoT environments.

<title>Abstract</title> For the joint scheduling problem of AGVs and machines in job shops, traditional scheduling methods are often constrained and difficult to adapt to complex production environments and demand changes. For this reason, this paper proposes a PPO algorithm based on two-dimensional action space to solve the joint scheduling problem of AGVs and machines in the job shop. First, the computation of the loss function is modified for the characteristics of the two-dimensional action space to ensure a stable learning performance of the policy gradient. Then, the PPO-Clip version of the objective function is used for policy updating. The experimental results of randomized arithmetic cases show that the PPO algorithm based on two-dimensional action space has better training effect and convergence performance on the joint scheduling problem of AGVs and machines in the job shop. Compared with traditional methods, the algorithm has a large improvement in the optimal solution for most instances. In scalability tests in large-scale scenarios, the 2D-PPO-based algorithm exhibits high solution efficiency and robustness, especially in maintaining consistency with the solution quality of the optimal scheduling rule.

A double-deck deep reinforcement learning-based energy dispatch strategy for an integrated electricity and district heating system embedded with thermal inertial and operational flexibility

Hardware accelerators (such as the Cell Broadband Engine) have recently received a significant amount of attention from the computational science community because they can provide significant gains in the overall performance of many numerical simulations at a low cost. However, such accelerators usually employ a rather unfamiliar and specialized programming model that often requires advanced knowledge of their hardware design. In this article, we demonstrate an alternate and simpler approach toward managing the main complexities in the programming of the cell processor, called software caching. We apply this technique to a numerical relativity (NR) application: a time-domain, finite-difference Kerr black hole perturbation evolver, and present the performance results. We obtain gains in the overall performance of generic simulations that are close to the theoretical maximum that can be obtained through our parallelization approach.

Back propagation (BP) is the default solution for gradient computation in neural network training. However, implementing BP-based training on various edge devices such as FPGA, microcontrollers (MCUs), and analog computing platforms faces multiple major challenges, such as the lack of hardware resources, long time-to-market, and dramatic errors in a low-precision setting. This article presents a simple BP-free training scheme on an MCU, which makes edge training hardware design as easy as inference hardware design. We adopt a quantized zeroth-order method to estimate the gradients of quantized model parameters, which can overcome the error of a straight-through estimator in a low-precision BP scheme. We further employ a few dimension reduction methods (e.g., node perturbation, sparse training) to improve the convergence of zeroth-order training. Experiment results show that our BP-free training achieves comparable performance as BP-based training on adapting a pre-trained image classifier to various corrupted data on resource-constrained edge devices (e.g., an MCU with 1024-KB SRAM for dense full-model training, or an MCU with 256-KB SRAM for sparse training). This method is most suitable for application scenarios where memory cost and time-to-market are the major concerns, but longer latency can be tolerated.

This paper introduces control requirements, control method choosing, hardware design and software for the automatic mixture system of magnesia refractory bricks. S7–200 series of PLC are used to realize automatic control for batching system. Because of complexity of automatic mixture system, conventional compensating control method can not meet the required question precisely. A kind of mixture control system, based on dynamic neural network, is designed through analyzing the influence precision factors of mixture. Simulation is studied by collecting the mixture historical data from field engineering. And the simulation results illustrate that the method can reduce the mixture error effectively.