Data Capture via High Speed ADCs Using FPGA

Software defined radio (SDR) is a vast and emerging field that requires the design of various technologies such as antenna, RF, IF, and digital baseband subsystems. Among all these technologies, data converters that convert signals between analog and digital domains are highly crucial. On the other hand field programmable gate arrays (FPGAs) based platforms are being preferred for evaluating and implementing the digital communication concepts due to their programmability and reconfigurability. As a result they are well suited for the design of SDR technology. In this research work, we develop a platform where high-speed data converters are interfaced with high performance FPGAs. Interfaces are designed for analog-to-digital convertors (ADC) and digital-to-analog convertors (DAC) to communicate with FPGAs. For the interface design between ADC and FPGA, a double data rate and a low voltage differential signalling based serial output is adopted. And, for the interface design between DAC and other FPGA, parallel complementary metal oxide semiconductor outputs are used. To reconfigure the modes and parameters of the data convertors, serial peripheral interface data controllers have been designed. We have through simulations evaluated the performance of our designed interfaces between data convertors and FPGAs.

The soft computing algorithms are being nowadays used for various multi input multi output complicated non linear control applications. This paper presented the development and implementation of back propagation of multilayer perceptron architecture developed in FPGA using VHDL. The usage of the FPGA (Field Programmable Gate Array) for neural network implementation provides flexibility in programmable systems. For the neural network based instrument prototype in real time application. The conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGA have higher speed and smaller size for real time application than the VLSI design. The challenges are finding an architecture that minimizes the hardware cost, maximizing the performance, accuracy. The goal of this work is to realize the hardware implementation of neural network using FPGA. Digital system architecture is presented using Very High Speed Integrated Circuits Hardware Description Language (VHDL)and is implemented in FPGA chip. MATLAB ANN programming and tools are used for training the ANN. The trained weights are stored in different RAM, and is implemented in FPGA. The design was tested on a FPGA demo board. Keywords- Backpropagation, field programmable gate array (FPGA) hardware implementation, multilayer perceptron, pressure sensor, Xilinx FPGA.

Nowadays the need for dealing with ultra-high speed Analog to Digital Converter (ADC) is becoming more and more common, from Telecommunications to Precise Instrumentation, every application is increasing the analog to digital interface data rate. The ultra-high sampling rate of the ADCs demands the use of advanced acquisition techniques as well as the latest technology available. The utilization of dedicated Application Specific Integrated Circuit (ASIC) is an expensive solution to deal with the very high throughput from the ADC and its lack of flexibility is a huge drawback. On the other hand, the technology, the architecture and the state-of-the art of the current Field Programmable Gate Arrays (FPGAs) make them especially suitable to act as interface between an ultra-high speed ADC and a data processing unit. Another extra advantage is the reconfigurability of the FPGAs, they can be quickly adapted to different ADCs or different data processing units. The purpose of this paper is to present a practical approach to interface an ultra-high speed 8-bit ADC, MAX104, from Maxim Integrated Circuit, which performs digitalization of the input signal with a sampling rate of 1Gsps and a commercial and popular FPGA, the Virtex2 Pro, from Xilinx Corporation. Once the ADC digital data have been acquired, then they can be processed by either the dedicated FPGA Digital Signal Processing (DSP) blocks, or the FPGA embedded processors or just send the data out to a PC for later processing. Hence, the proposed method of implementation can be used as front-end of a wide range of applications.

With the rapid development of electronic science and technology, the signal frequency that engineers need to measure becomes higher and higher. Limited by the analog-to-digital converter (ADC) sampling rate and Nyquist sampling theorem, the digital oscilloscope can only measure waveform in a very limited range of frequency in real-time sampling mode. Therefore, it is necessary to introduce an equivalent sampling technique to increase the ability of the oscilloscope to measure higher frequency signals. In this paper, a random equivalent sampling reconstruction method based on field programmable gate array (FPGA) is proposed. In the random equivalent sampling mode, multiple sets of samples collected by the ADC are buffered in the FPGA, and the stretched circuit measures the time interval $\Delta$t between each set of trigger signals and the rising edge of the first sampling clock. Through these samples as well as the $\Delta$t in each group, the waveform can be reconstructed in FPGA, and then this reconstructed waveform can be read and displayed by the upper computer. The waveform refreshing rate of the random equivalent sampling can be greatly improved by this kind of reconstruction inside a FPGA.

Present days witnessed extensive use of Analog to Digital Converters (ADC) in different fields of applications, as an interface between the analog world and the digital world. However, in most cases, external ADCs are employed to meet the purpose. This eventually makes the system bulky, power-consuming, complex, and costly. Implementation of reconfigurable ADC programmed inside Field-Programmable Gate Array (FPGA) could reduce the system cost and power consumption substantially. Furthermore, this will make the system simple as it does not require any external circuitry for the conversion of analog input data into digital form for processing. Thus, in this paper, a multichannel reconfigurable ADC is designed, with an additional feature of time multiplexing for efficient data acquisition. The design is being implemented using 100MHz FPGA clock frequency thus can achieve a sampling rate of 100 MS/s with a resolution of 10bit for 0-2.5V signal range. The FPGA resource utilization for the complete ADC model consists of 341 FFs and 265 LUTs, with total on-chip power consumption of 14.428 W. The proposed system can also be implemented for different analog signal from transducers, depending upon the demand and requirement of sensing parameters the data collection time can be varied for transducer to transducer.

Usage of digital receivers in today's radar and electronic warfare applications is becoming more common. Analog to digital converters (ADC) used in digital receivers play a significant role in the performance of these receivers. Therefore, it is very important to obtain performance analysis of possible ADC's under different conditions such as different temperature etc. before making final decision of the ADC to be used in the digital receiver. It is obvious that it would be very helpful to get results of integration of different ADC's with the existing system and to test ADC's under different conditions that may not exist on data sheets. For this reason, a Field Programmable Gate Array (FPGA) based board is designed in order to gather digital output of ADC being evaluated and a graphical analysis software responsible for analyzing gathered digital output is developed. Developed infrastructure enables us to compare performances of different ADC's in the same system and in same conditions by replacing only the ADC to be analyzed.

Lightweight implementation of security primitives, e.g., physical unclonable functions (PUFs) and true random number generator, in field programmable gate array (FPGA) is crucial replacement of the conventional decryption key stored in battery-backed random access memory or E-Fuses for the protection of field reconfigurable assets. A slice is the smallest reconfigurable logic block in an Xilinx FPGA. The entropy exploitable from each slice of an FPGA is an important factor for the design of security primitives. Previous research has shown that the locations of slices can impact the quality of delay-based PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (Pi-coPUF) cells that can each be fully fitted into a single slice are evaluated. To accurately evaluate their statistical performance, data from a large number of devices are required. To this end, 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale comprehensive analysis for the two designs. This is the first time single-slice disorder-based security entities have been investigated and compared on 28-nm Xilinx FPGA. Uniqueness, uniformity, correlation, reliability, bit-aliasing and min-entropy of each type of cell are evaluated for four different types of cell placement. Our experimental results corroborate that the location of both cell types in the FPGA affects their performances. For both cell types, the lower the correlation between devices, the higher the min-entropy and uniqueness. Overall, the min-entropy, correlation and uniqueness of PicoPUF are slightly higher than those of RO. Otherwise, the uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower than those of the RO. Comparing the resource usage and metrics of the PicoPUF, ring oscillator PUF and some existing memory-based PUF implementations, PicoPUF stands out as a lightweight FPGA-based weak PUF design. The raw data for the PicoPUF design are made publicly available to enable the research community to use them for benchmarking and/or validation.

The use of an automated Data Acquisition System (DAS) is very important in testing and measurement systems. The desire is extremely high in the DAS with high speed, multi-channel, and large capacity, so research in this area becomes very significant. The growing problem in DAS is to acquire the data with the required data rate and store data onto the on-chip memory. Microcontroller, microprocessor or Digital Signal Processors (DSP) devices can be programmed as a DAS, but these devices comprise problems, such as slower data acquisition rates, nonavailability of sufficient on-chip memory, etc. To overcome these above drawbacks, this paper provides an approach to design and develop DAS based on the Field Programmable Gate Array (FPGA). To acquire the data from Analog to Digital Converter (ADC) to FPGA, an Inter Integrated Circuit (I2C) serial communication protocol is used. I2C master communication protocol is designed and developed using VHDL with the Quartus II version 13.1, and the I2C master protocol is implemented in cyclone III FPGA. FPGA is acting as a master controller. DAS with the FPGA will provide the better acquisition results compared to the existing acquisition system.

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The effort in reducing the area of AES implementations has largely been focused on Application-Specific Integrated Circuits (ASICs) in which a tower field construction leads to a small design of the AES S-box. In contrast, a naive implementation of the AES S-box has been the status-quo on Field-Programmable Gate Arrays (FPGAs). A similar discrepancy holds for masking schemes – a wellknown side-channel analysis countermeasure – which are commonly optimized to achieve minimal area in ASICs.In this paper we demonstrate a representation of the AES S-box exploiting rotational symmetry which leads to a 50% reduction of the area footprint on FPGA devices. We present new AES implementations which improve on the state of the art and explore various trade-offs between area and latency. For instance, at the cost of increasing 4.5 times the latency, one of our design variants requires 25% less look-up tables (LUTs) than the smallest known AES on Xilinx FPGAs by Sasdrich and Guneysu at ASAP 2016. We further explore the protection of such implementations against first-order side-channel analysis attacks. Targeting the small area footprint on FPGAs, we introduce a heuristic-based algorithm to find a masking of a given function with d + 1 shares. Its application to our new construction of the AES S-box allows us to introduce the smallest masked AES implementation on Xilinx FPGAs, to-date.

This paper explores the use of the Xilinx's system generator development tool for the implementation of control algorithms on Xilinx field programmable gate arrays (FPGA). The Simulink plug in complements traditional hardware description language (HDL) by providing a graphical language with a higher level of abstraction for the development of FPGA designs. After taking into consideration the challenges of converting control designs that have been implemented and verified within the Simulink environment to FPGA hardware implementation, a systematic approach is presented. As a case study, a FPGA implementation of a control system was derived and verified for a simulated unmanned ground vehicle (UGV). The design example demonstrates the validity of the presented method as an efficient and reliable method for rapid system prototyping for designs developed using the Simulink environment.

Compared with the four-phase optical structure, the grating encoder based on two-phase optical structure reduces the number of optical devices used in the system and makes the system more compact. Due to the high requirements for realtime and parallel processing of algorithm solution, the powerful parallel computing ability of Field Programmable Gate Array (FPGA) and customized hardware acceleration algorithm are needed to improve the real-time performance. In the previous research, the displacement signal generated by the grating encoder can be input into the FPGA through analog to digital converter (ADC) sampling, and then complete self-designed filter filtering, phase correction and displacement solution. In this paper, further, the ADC sampling rate adjustable interface is added to the FPGA, the global signal and the dc offset remove algorithm is added, and the displacement solution results in the form of fixed-point number are output to the host computer through the MicroBlaze (MB) soft core. MB core can realize process control and interface conversion on FPGA, and use a small amount of logic resources to replace the functions of MCU and DSP of traditional embedded measurement system, so as to further improve the integration of the instrument. A series of experiments are carried out on the two-phase FPGA platform. ADC sampling rate is 200ksps, 8-Channel synchronous parallel sampling, FPGA system clock frequency is 200MHz. The linear displacement table is set to drive the measurement grating at different displacement speeds, and the total stroke is set to 10mm. The FPGA real-time displacement solution platform is tested. The experimental results show that FPGA obtains accurate displacement solution results under different speed tests. In the test of 2 mm/s, the maximum cumulative displacement measurement error is 5um, which shows the real-time performance and accurate displacement solution performance of FPGA platform.

Recently, many researches have investigated efficient reverse engineering methods to restore Programmable Logic Points (PLPs) and Programmable Interconnect Points (PIPs) in SRAM-based Field Programmable Gate Arrays (FPGAs). However, the research on the restoration of Programmable Content Points (PCPs) such as memory data are rarely studied. In this paper, we propose an efficient reverse engineering method to recover Read Only Memory (ROM) data, which is essential for the implementation of modern digital circuits. First, we analyze the FPGA hardware resources mapped to Xilinx primitive library of ROM, and next the proposed reverse engineering process is explained using mapping relation between ROM data and hardware resources. As an example, XC3S50 FPGA of Xilinx Sparatan-3 family is utilized, and the process of restoring the SBOX of AES (Advanced Encryption Standard) is provided as a practical application.

This paper describes a flexible and systematic implementation method of Petri Nets that can be applied to high speed parallel control. This paper suggests a hard-wired implementation for a high frequency clock-driven system with little jitter. To implement Petri Nets with synchronous (clock-driven) digital circuits, a Synchronous Petri Net is proposed. The suggested implementation method is based on a regular cell-array such as FPGA (field programmable gate array). Radix-k Petri Net and Radix-k conversion are defined to solve technology mapping problem of FPGA that consists of k-size cells. Cell usage, cell utilization, cell complexity, and speed index are defined and derived, which are used for quantitative analysis and efficient design. To help the design process, necessary CAD tools such as design entry library, hard-macro library, and net-list converter are developed. The suggested method is demonstrated using Xilinx FPGA, and its operation is verified by computer simulations.

This study proposed a novel Field Programmable Gate Array (FPGA)-based 32-channel data acquisition system to acquire and process Electroencephalography (EEG) signal. The data acquisition system utilized PYNQ-Z1 board, which was equipped with a Xilinx ZYNQ XC7Z020-1CLG400C All Programmable System-on-Chip (APSoCs) that offered high performance embedded system because of the combination between the flexibility and versatility of the programmable logic (PL) and the high-speed embedded processor or programmable system (PS). As the core of the data acquisition system, the FPGA collected, processed, and stored the data based on Front-End Analog to Digital Converter (ADC) ADS1299EEG-FE. The communication protocol used in the data acquisition system was Serial Peripheral Interface (SPI) with daisy-chain configuration. For the signal processing part, a 5th-order Butterworth bandpass filter and Fast Fourier Transform (FFT) has been implemented directly on the PYNQ’s Overlay. The overlay was configurable FPGA design that extend the system from the PS of the ZYNQ to the PL, enabling us to control directly the hardware platform using Python running in the PS. The mean accuracy error obtained from validation result of the developed system was 1.34% and the Total Harmonic Distortion (THD) performance criterion resulting in 0.0091%, both of them validated with NETECH MiniSIM EEG Simulator 330. The comparison between the developed system and Neurostyle NS-EEG-D1 System acquiring the same EEG data shows correlation parameter gradient of 0.9818, y-intercept with -0.1803, and R squared of 0.9742 based on the least square analysis. The parameter above indicated that the developed system was adequate enough, if not on a par, with the commercialized, medical grade EEG data acquisition system Neurostyle NS-EEG-D1 as the system assured and maintained accuracy with higher sampling frequency.