Data Encryption on GPU for High-Performance Database Systems

Graphics processing units have proved their capability for general-purpose computing in many research areas. In this paper, we propose the mechanism and implementation of a database system that encrypts and decrypts data by using GPU. The proposed mechanism is mainly designed for database systems that require data encryption and decryption to support high security level. The outsourced database systems or database cloud service could be a good candidate for our system. By exploiting the computation capability of GPU, we achieve not only a fast encryption and decryption time per operation, but also a higher overall performance of a database system by offloading computation to GPU. Moreover, the proposed system includes a mechanism which can decide whether to offload computation to GPU or not for more performance gain. We implemented the AES algorithm based on CUDA framework and integrate with MySQL, a commodity database system. Our evaluation demonstrates that the encryption and decryption on GPU show eight times better performance compared to that on CPU when the data size is 16 MB and the performance gain is proportional to the data size. We also show that the proposed system alleviates the utilization of CPU, and the overall performance of the database system is improved by offloading heavy encrypting and decrypting computation to GPU.

Performance in database systems is strongly influenced by buffer management and transaction recovery methods. This paper presents the principles of the database cache, which replaces the traditional buffer. In comparison to buffer management, cache management is more carefully coordinated with transaction management, and integrates transaction recovery. High throughput of small- and medium-sized transactions is achieved by fast commit processing and low database traffic. Very fast handling of transaction failures and short restart time after system failure are guaranteed in such an environment. Very long retrieval and update transactions are also supported.

Watershed analysis, as a fundamental component of digital terrain analysis, is based on the Digital Elevation Model (DEM), which is a grid (raster) model of the Earth surface and topography. Watershed analysis consists of computationally and data intensive computing algorithms that need to be implemented by leveraging parallel and high-performance computing methods and techniques. In this paper, the Multiple Flow Direction (MFD) algorithm for watershed analysis is implemented and evaluated on multi-core Central Processing Units (CPU) and many-core Graphics Processing Units (GPU), which provides significant improvements in performance and energy usage. The implementation is based on NVIDIA CUDA (Compute Unified Device Architecture) implementation for GPU, as well as on OpenACC (Open ACCelerators), a parallel programming model, and a standard for parallel computing. Both phases of the MFD algorithm (i) iterative DEM preprocessing and (ii) iterative MFD algorithm, are parallelized and run over multi-core CPU and GPU. The evaluation of the proposed solutions is performed with respect to the execution time, energy consumption, and programming effort for algorithm parallelization for different sizes of input data. An experimental evaluation has shown not only the advantage of using OpenACC programming over CUDA programming in implementing the watershed analysis on a GPU in terms of performance, energy consumption, and programming effort, but also significant benefits in implementing it on the multi-core CPU.

Data parallel programming provides an accessible model for exploiting the power of parallel computing elements without resorting to the explicit use of low level programming techniques based on locks, threads and monitors. The emergence of Graphics Processing Units (GPUs) with hundreds or thousands of processing cores has made data parallel computing available to a wider class of programmers. GPUs can be used not only for accelerating the processing of computer graphics but also for general purpose data-parallel programming. Low level data-parallel programming languages based on the Compute Unified Device Architecture (CUDA) provide an approach for developing programs for GPUs but these languages require explicit creation and coordination of threads and careful data layout and movement. This has created a demand for higher level programming languages and libraries which raise the abstraction level of data-parallel programming and increase programmer productivity. The Accelerator system was developed by Microsoft for writing data parallel code in a high level manner which can execute on GPUs, multicore processors using SSE3 vector instructions and FPGA chips. This paper compares the performance and development effort of the high level Accelerator system against lower level systems which are more difficult to use but may yield better results. Specifically, we compare against the NVIDIA CUDA compiler and sequential C++ code considering both the level of abstraction in the implementation code and the execution models. We compare the performance of these systems using several case studies. For some classes of problems, Accelerator has a performance comparable to CUDA, but for others its performance is significantly reduced; however in all cases it provides a model which is easier to use and enables greater programmer productivity.

The performance of database systems is usually characterised by their average-case (i.e., throughput) behaviour in standardised or de-facto standard benchmarks like TPC-X or YCSB. While tails of the latency (i.e., response time) distribution receive considerably less attention, they have been identified as a threat to the overall system performance: In large-scale systems, even a fraction of requests delayed can build up into delays perceivable by end users. To eradicate large tail latencies from database systems, the ability to faithfully record them, and likewise pinpoint them to the root causes, is imminently required. In this paper, we address the challenge of measuring tail latencies using standard benchmarks, and identify subtle perils and pitfalls. In particular, we demonstrate how Java-based benchmarking approaches can substantially distort tail latency observations, and discuss how the discovery of such problems is inhibited by the common focus on throughput performance. We make a case for purposefully re-designing database benchmarking harnesses based on these observations to arrive at faithful characterisations of database performance from multiple important angles.KeywordsDatabase benchmarksTail latenciesBenchmark harness

Previous research in the field of statistical testing of random number sequences using Graphics Processing Units (GPU) [1] has shown that this approach yields a significant increase in performance for a subset of the statistical tests proposed by National Institute of Standards and Technology (NIST) [2]. The present paper aims at further improvements in the performance of statistical testing of random number sequences, by focusing on another technology dedicated to GPU computing, the Compute Unified Device Architecture (CUDA). CUDA extends the C programming language with functionality for massively parallel programming on GPUs. Due to the flexibility given by the CUDA memory and thread model plus the optimizations that take advantage of the Parallel Data Cache, we were able to further improve the performance of the statistical testing algorithms proposed by NIST. Experimental results show speedups of up to 219, depending on the test and the size of the input data, with an overall average speedup of 51.

Machine virtualization and cloud computing environment have highlighted for last several years. This trend is based on the endeavor to enhance the utilization and reduce the ownership cost of machines. On the other hand, in aspect of high performance computing, graphics processing unit (GPU) has proved its capability for general purpose computing in many research areas. Evolving from traditional APIs such as the OpenGL and the Direct3D to program GPU as a graphics device, the CUDA of NIVDIA and the OpenCL provide more general programming environment for users. By supporting memory access model, interfaces to access GPUs directly and programming toolkits, users can perform parallel computation using the hundreds of GPU cores. In this paper, we propose a GPU virtualization mechanism to exploit GPU on virtualized cloud computing environment. Differently from the previous work which mostly reimplemented GPU programming APIs and virtual device drivers, our proposed mechanism uses the direct pass-through of PCI-E channel having GPU. The main limitation of previous approaches is virtualization overhead. Since they were focused on the sharing of GPU among virtual machines, they reimplemented GPU programming APIs at virtual machine monitor (VMM) level, and it incurred significant performance overhead. Moreover, if APIs are changed, they need to reengineer the most of APIs. In our approach, bypassing virtual machine monitor layer with negligible overhead, the mechanism can achieve similar computation performance to bare-metal system and is transparent to the GPU programming APIs.

The commoditization of high-performance networking has sparked research interest in the RDMA capability of this hardware. One-sided RDMA primitives, in particular, have generated substantial excitement due to the ability to directly access remote memory from within an application without involving the TCP/IP stack or the remote CPU. This paper considers how to leverage RDMA to improve the analytical performance of parallel database systems. To shuffle data efficiently using RDMA, one needs to consider a complex design space that includes (1) the number of open connections, (2) the contention for the shared network interface, (3) the RDMA transport function, and (4) how much memory should be reserved to exchange data between nodes during query processing. We contribute six designs that capture salient trade-offs in this design space. We comprehensively evaluate how transport-layer decisions impact the query performance of a database system for different generations of InfiniBand. We find that a shuffling operator that uses the RDMA Send/Receive transport function over the Unreliable Datagram transport service can transmit data up to 4× faster than an RDMA-capable MPI implementation in a 16-node cluster. The response time of TPC-H queries improves by as much as 2×.

Turbo Similarity Searching (TSS) is a two phases searching procedure that has been proven by previous works as one of the best searching method on chemical databases. TSS however consumes lots of computation time due to the number of searches and fusion carried out in the second phase of its procedure. Hence, TSS would not be able to cater the increase in the chemical database size due to this limitation. With the emergence of the parallel technology, this research looks into accelerating TSS on the widely-used many-cores i.e. the Graphics Processing Unit (GPU) and multi-cores platform. This would not only solve the computational time issue but also the cost as GPUs can be obtained at a lower cost. Hence, the implementation of TSS will help the medicinal chemist to execute the virtual screening in an accurate and fast manner. This study investigates the best possible method to parallelize TSS via experimentation of three parallel designs; two designs were implemented on GPU platform using the Compute Unified Device Architecture (CUDA) API namely CUDA 1 and CUDA 2 whilst one design was implemented on multi-core platform using OpenMP API. The CUDA 1 design had shown tremendous speedup and low GPU-memory utilization as compared to CUDA 2 design. In general observation, the parallel CUDA 1 was 131 times faster than sequential and 51 times faster than parallel OpenMP. This leads to the conclusion that CUDA 1 design as the best parallel design for TSS.

The authors presents performance analysis of a concurrent file reorganization algorithm. They examined the effect of buffer size, degree of reorganization, and write probability of transactions on system throughput. The problem of file reorganization considered involves altering the placement of records on pages on a secondary storage device. This reorganization must be done in-place. The approach is appropriate for a non-in-place reorganization. The motivation for such a physical change is to improve the database system's performance, by minimizing the number of page accesses made in answering a set of queries. It is shown through simulation that the algorithm, when run concurrently with user transactions, provides an acceptable level of overall database system performance. >

Enhancing query processing on stock market cloud-based database

Implementation of Image Enhancement Algorithms and Recursive Ray Tracing using CUDA

Based on the principle of QR loop iterations, this paper implements a parallel algorithm based on the hardware of GPU (Graphic Process Unit) by using routines from CUDA (Computer Unified Device Architecture) to find the eigenvalues of general matrices. CPU and GPU computing card form a client-server computing framework. Here, CPU can be regarded as a client and GPU card is considered as a computing server. For the experiment environment, this paper chooses a GPU card with the model of NVIDIA GeForce GTX460 as a server side and a CPU with the model of Intel Core i5-760 quad-core as a client side. Win7 64-bit is selected as the operating system. The parallel implementation consists of two parts:PA H and PA QR. PA H is a procedure that transforms a matrix A into the Hessenberg matrix B. PA QR is the actual parallel algorithm of the QR iterations that is imposed on the Hessenberg matrix B for finding eigenvalues of the general matrix A. The speedup ratio of the proposed algorithm is jarless when the number of iterations becomes greater. The experimental results show that the parallel implementation with CUDA on GPU only makes use of less running time than traditional sequential algorithms. The speedup ratio of PA H is between 1.79 and 7.81. The speedup ratio of PA QR is between 3.24 and 118.9. Especially, when the order of general matrix equals 8192, the amount of iterations becomes 10000. The speedup ratio of the PA-H and the PA QR can run up to 7.81 and 118.9 respectively.

The small slop approximation (SSA) is an accurate method to calculate the electromagnetic (EM) scattering properties of rough surfaces. However, its computational complexity restricts its application to smaller domains and there is always the need for speedup in very large cases using pure central processing units (CPUs) hardware. With the development of graphics processing units (GPUs), more processors are dedicated to perform independent calculations. In addition, NVIDIA introduced a parallel computing platform, compute unified device architecture (CUDA), which provides researchers an easy way to use processors on GPU. To calculate EM scattering properties on GPU, we reformulate the SSA method with CUDA to take advantage of GPU threads. Because each thread executes synchronously and deals with a corresponding point data of rough surface, the CUDA-based SSA method calculates faster than the pure-CPU equivalent. To overcome memory limitations, the data of large rough surface are stored on hard disk. Moreover, a subsidiary thread is used to deal with the process of data transmission between the memory and the hard disk and reduce transmitting time further. The factors, block size, data transfers, and register, are also discussed in the optimization of the CUDA application. Test cases running on a NVIDIA GTX 460 GPU indicate that two orders of magnitude speedup, including file input and output, is obtained with our new formulation.

Many-core framework, represented by Graphic Processing Unit (GPU), has been becoming more popular in scientific computing and data analysis, and Compute Unified Device Architecture (CUDA) allows developers to carry out computation on GPUs more conveniently. Matrix operation is one of the most important application scenarios of GPU computation and CUDA, widely appearing in domains like graph applications and artificial intelligence. This paper focuses on accelerating matrix power operation (MPO) process, which appears in many engineering problems and may be time-consuming when the scale of matrixes is large, with GPUs and CUDA. In this paper, three techniques are used to speed up the MPO process: matrix parallel reduction, matrix parallel multiplication and CUDA dynamic parallelism. The experiments were carried out on NVIDIA RTX 2080 Super and Intel(R) Core(TM) i7-10750H. The code is compiled and executed in Visual Studio 2019 community, the GPU driver version is 461.40, the CUDA version is 11.1, and the NVCC version is 11.1.74. With all three techniques, the MPO process can get hundreds of times speedup compared with the sequential multiplication process executed by Eigen library, even though the code of algorithm is hardly optimized. Moreover, with the number of power increasing, the efficiency of algorithm can be even higher because of the relatively fixed time consumed in data transmission and GPU memory allocation.