Data Hiding in Digital Image for Efficient Information Safety Based on Residue Number System

PurposeThe privacy of the information is a major challenge in the communication process. In the present modern generation, the cryptography plays a vital role in providing security for data, such as text, images and video while transmitting from source to destination through internet or intranet. The Rivest-Shamir-Adleman (RSA) is an asymmetric key cryptographic system, where the security of the method works on the strength of the key.Design/methodology/approachIn an asymmetric key crypto system, a pair of keys is generated one public key for encryption and one private key for decryption. The major challenge of implementing the RSA is the power function which becomes tedious and time consuming as the exponential value increases. The Chinese remainder theorem proves to be the best for data encryption when it comes to execution time of the algorithm. The proposed novel RSA algorithm with lookup table (LUT) is an extension to the Chinese remainder algorithm, which works better for image and video in terms of time complexity.FindingsThis paper presents a LUT approach for implementing the RSA with a minimal processing time. The proposed algorithm was compared with the standard algorithms like, Chinese remainder theorem, binary approach and squared multiplication approach. As the size of the exponent value increases, the proposed method shows better performance compared to other standard methods.Originality/valueThis paper presents a LUT approach for implementing the RSA with a minimal processing time. The proposed algorithm was compared with the standard algorithms like, Chinese remainder theorem, binary approach and squared multiplication approach. As the size of the exponent value increases, the proposed method shows better performance compared to other standard methods.

This study basically do image management processes which have no restrictions in about permissions to view the images on the XYZ consultant. This results in image can be easily used by those who do not have the right to open it. Therefore, security research digital image with cryptographic techniques using Rivest Shamir-Adleman With the Chinese Remainder Theorem (RSA-CRT) aims to provide restrictions permissions to view the image, and give the number of restrictions to view images that can be performed by the client. Results of this research is a security application that can create digital images can not be seen without using a specific key and restrictions as well as providing an image to only be opened in a few times. Index Terms” Cryptography, Digital Image, RSACRT, Data Security, Asymmetric Key

In order to get an efficient comprehensive analysis on Doppler estimation in RADAR; need an enhanced arithmetic formulation procedure for density, power and latency optimisations. Modular adders and multipliers are very crucial components in the performance of residue number system-based applications. The Residue Number System (RNS) is a non-positional number system that allows parallel computations without transfers between digits. However, some operations in RNS require knowledge of the positional characteristic of a number. Among these operations is the conversion from RNS to the positional number system. The methods of reverse conversion for general form moduli based on the Chinese remainder theorem and the mixed-radix conversion are considered, as well as the optimized methods for special form moduli. A modified New CRT-I & New CRT-II with conjugate moduli set is considered to implement adder, multipliers and subtractions with optimised algorithms. This paper mainly deals with the conversion of numbers from binary to RNS as well RNS to binary with the specific modulo {2^n±k} which proves this new method. Modified Radix16 booth encoding algorithm and square carry bypass adder are used in implementation of RNS system to reduce parameter constraints.

Public‐key cryptosystems such as elliptic curve cryptography (ECC) and Rivest–Shamir–Adleman (RSA) are widely used for data security in computing systems. ECC provides a high level of security with a much smaller key than RSA, which makes ECC a preferred choice in many applications. This study proposes a multi‐key ECC based on the residue number system. The proposed architecture employees deep pipelining to allow the concurrent encryption of 21 keys. The proposed architectures are implemented on two different field programmable gate array (FPGA) platforms and results are compared with existing ECC architectures. The proposed implementation on Virtex‐7 FPGA achieves a throughput of 1816 kbps at a clock frequency of 73 MHz.

In this modern world of Internet and with the development of digital communication and multimedia application, image security has become an important concern in storage and communication. A cryptography technique provides good strength for securing and protecting images essentially in the fields as medical, law enforcement and military. Reversible watermarking provides authentication, in which original image and watermark gets recovered. In this paper, Initially, secrete image is passed through S-DES (Simple-Data Encryption Standard) using a key image, then this encrypted image is watermarked using a watermark image and a position matrix, this watermarked image is passed through RNS (Residue Number System) and finally we get our DES watermarked RNS encoded image. For decoding, we have to go in reverse order, i.e. initially reverse RNS (CRT, Chinese Remainder Theorem) followed by watermark and S-DES encoded image extraction and hence our secrete image back.

Long period pseudo-random sequence plays an important role in modern information processing systems. Base on residue number system (RNS) and permutation polynomials over finite fields, a pseudorandom sequence generation scheme is proposed in this paper. It extends several short period random sequences to a long period pseudo-random sequence by using RNS. The short period random sequences are generated parallel by the iterations of permutation polynomials over finite fields. Due to the small dynamic range of each iterative calculation, the bit width in hardware implementation is reduced. As a result, we can use full look-up table (LUT) architecture to achieve high-speed sequence output. The methods to find proper permutation polynomials to generate long period sequences and the optimization algorithm of Chinese remainder theorem (CRT) mapping are also proposed in this paper. The period of generated pseudorandom sequence can exceed 2100 easily based on common used field programmable gate array (FPGA) chips. Meanwhile, this scheme has extensive freedom in choosing permutation polynomials. For example, 10905 permutation polynomials meet the long period requirement over the finite field F q with q ≢ 1(mod 3) and q ⩽ 503. The hardware implementation architecture is simple and multiplier free. Using Xilinx XC7020 FPGA chip, we implement a sequence generator with the period over 250, which only costs 20 18kb-BRAMs (block RAM) and a small amount of logics. And the speed can reach 449.236 Mbps. The National Institute of Standards and Technology (NIST) test results show that the sequence has good random properties.

The architecture of a fault-tolerant modular neurocomputer based on modular number projections

Huge storage volume is one of the main bottlenecks for the development of blockchain, so how to release the burden by optimizing the storage mechanism has become an important problem. Most of the current solutions would modify the architecture of blockchain, which weakens the characteristics of the decentralization, such as cloud storage. In this paper, a storage optimization mechanism based on residual number system is proposed to reduce the storage volume on each node. In addition, the recovery procedure of CRT-II (The new Chinese Remainder Theorem) is used to detect garbled data from devil nodes, which enable the proposed storage mechanism with strong fault tolerance capability. Both theoretical analysis and simulation results prove the effectiveness and reliability of the proposed scheme.

The carry-free nature of the residue number system (RNS) has made it attractive for implementing a variety of specialized high-performance digital signal processing systems. A new implementation of a high-speed residue-to-binary converter based on the Chinese Remainder Theorem (CRT) is proposed. It employs a new r-operand adder modulo M, realized using carry-save adders and its delay path involves only one addition of two a-bit operands performed by some carry-propagate adder, where M is the dynamic range and a=[log/sub 2/ M]. The latter feature is in contrast with any other CRT-based converter that has been proposed to date, which require two subsequent additions of a-bit operands. This circuit offers a latency period significantly smaller than the fastest known designs. >

In Residue Number System (RNS), a large integer is represented as a set of smaller integers called residues. Redundant Residue Number System (RRNS) is obtained by adding some redundant residues which brings in error detection and error correction capability. This capability makes RRNS a promising way to provide a very fast arithmetic in the field of digital computers. At the receiver, RRNS codes are decoded using Chinese Remainder theorem (CRT). An alternative scheme called Mixed Radix Conversion (MRC) is also used which results in low decoding complexity when compared to CRT. This paper presents a single bit error correction algorithm using RRNS. This algorithm doesn't require table lookup which helps to save memory during implementation. Representative examples are given.

In the last years, investigation on residue number systems (RNS) has targeted parallelism and larger dynamic ranges. In this paper, we start from the moduli set {2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> ,2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -1,2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1,2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(</sup> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1)/2+1,2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(</sup> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1)/2+1} , with an equivalent 5 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -bit dynamic range, and propose horizontal and vertical extensions in order to improve the parallelism and increase the dynamic range. The vertical extensions increase the value of the power-of-2 modulus in the five-moduli set. With the horizontal extensions, new six channel sets are allowed by introducing the 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1+1 or 2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -1+1 moduli. This paper proposes methods to design memoryless reverse converters for the proposed moduli sets with large dynamic ranges, up to (8 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> +1)-bit. Due to the complexity of the reverse conversion, both the Chinese Remainder Theorem and the Mixed Radix Conversion are applied in the proposed methods to derive efficient reverse converters. Experimental results suggest that the proposed vertical extensions allow to reduce the area-delay-product up to 1.34 times in comparison with the related state-of-the-art. The horizontal extensions allow larger and more balanced moduli sets, resulting in an improvement of the RNS arithmetic computation, at the cost of lower reverse conversion performance.

Computer networks by providing data exchange capability between connected systems are driving a revolution in digital world. However, by improving the technology and producing low price devices, the number of connected devices is rapidly growing, and users are moving from one computer per person to multidevices per person including cell phones, home appliances, and wearable gadgets which are all connected to the internet. Therefore, new network concepts and also challenges have been introducing to overcome issues of rapid growth of the number of connected devices. Moreover, for future network with huge number of members more complex processors are needed to perform required process. Therefore, researchers of these fields should look for novel methods to overcome distinct emerging challenges. Recently, residue number system (RNS) as an alternative method to reduce network operations overhead attracts network researchers. The RNS has been used as a tool to reduce transmission energy and increase reliability in wireless sensor networks. Moreover, RNS can enhance switching process, and substitute lookup tables with simple modular operations in software-defined network. This chapter presents different types of RNS applications in computer networks in order to familiar researchers with these concepts.

In information security, image steganography is one of the information securing process. Image steganography is mostly used in medical fields for hiding medical prescription data behind the medical images. Designing steganographic algorithms for empirical cover sources, such as digital images, is very perplexing due to the lack of accurate models. The most successful approach today avoids estimating the cover source distribution because this task is infeasible for complex and non-stationary sources. Instead, the steganography problem is formulated as source coding with fidelity constraint the sender entrenches the message with minimizing the distortion. Practical algorithms that entrench near the theoretical payload–distortion bound are available for a very general class of distortion functions. With the current framework, the only task left to the sender is essential for the design of the distortion function. Here information is which wants to be confidential that information's are stored behind the image pixels. However, due to increasing crypt analysis attacks and binary image de stenographic process image steganography has very less security. So improving the security in image steganography process, the current system provide the asymmetric encryption standard for improving more security in steganography.

@tj mod M, which is the fundamental operation in residue arithmetic. In addition, two hardware designs for efficient implementation of the algorithm and an application to Chinese Remainder Theorem (CRT) are developed. The proposed algorithm is fast and simple since it eliminates modulo arithmetic and the requirement of “whole word comparisons” in the operations. Instead, we take advantage of conventional binary carry save adders, simple bit checking, and dropping the overflow bits to efficiently implement the algorithm.We also introduced the use of carry save adders as our basic operation, thus shortening the iteration delays to a constant factor. Two hardware designs of the algorithm were discussed. The first approach uses minimal hardware resources with a time complexity of O(n), where the time unit is the delay of two carry save adders. The second hardware design is a tree structured systolic network which takes advantage of n duplicated cells to perform the same problem in O(log n) time. The CRT problem can be transformed into the problem of multiple summation modulo M by the table lookups with small address. Therefore it also can be computed in O(log n) time units by the tree structured systolic network where n is the number of moduli of the residue system.

Decoding in residue-number-system (RNS)-based architectures can be a bottleneck. A high-speed, flexible modulo decoder is an essential computational element to maintain the advantages of RNS. A fast and flexible modulo decoder, based on the Chinese remainder theorem (CRT), is presented. It decodes a set of residues into its equivalent representation in either unsigned magnitude or two's-complement binary number system. Two different architectures are analyzed: the first one uses carry-save adders, and the other uses modified structure carry-save adders. Both architectures are modular and are based on simple cells, which leads to efficient VLSI implementation. The decoder has a time complexity of theta (log N). >