DCT/IDCT processor for HDTV developed with dsp silicon compiler

In the paper “An analog 2-D DCT processor,” authors have presented a row-column method for computing 2-D discrete cosine transform (DCT). They have reported minimum peak signal-to-noise ratios (PSNR) 40.6 dB and 31.4 dB for 4-point and 8-point DCT, respectively. The main objective of this comment letter is to point out that those PSNR values are not correctly calculated. The actual minimum PSNR values are shown to be 24.7 dB and 22.7 dB for 4-point and 8-point DCT, respectively. Similarly, maximum PSNR values are corrected in this letter.

This paper proposes a high performance and low cost inverse discrete cosine transform (IDCT) processor for high definition Television (HDTV) applications by using cyclic convolution and hardwired multipliers. By properly arranging the input sequence, we formulate the one-dimensional (1-D) IDCT into cyclic convolution that is regular and suitable for VLSI implementation. The hardwired multiplier that implements multiplication with IDCT coefficients are first scaled and optimized by using the common sub-expression techniques. Based on these techniques, the data-path in the proposed two-dimensional (2-D) IDCT design costs 7504 gates plus 1024 bits of memory with 100 M pixels/sec throughput according to the cost estimation based on the cell library of COMPASS 0.6 μm SPDM CMOS technology. Also, we have verified that the precision analysis of the proposed 2-D 8 × 8 IDCT meets the demands of IEEE Std. 1180-1990. Due to the good performance in the computing speed as well as the hardware cost, the proposed design is compact and suitable for HDTV applications. This design methodology can be applied to forward DCT as well as other transforms like discrete sine transform (DST), discrete Fourier transform (DFT), and discrete Hartley transform (DHT).

The design of DCT (discrete cosine transform) circuits for HDTV (high-definition television) applications is addressed. Based on previous works on CCIR video image coding, several architectural solutions are presented and then compared. An optimization taking into account the potentials of present-day technologies and progress in arithmetic implementation and architecture makes it possible to implement a real-time DCT for HDTV implementation in roughly 40 mm/sup 2/ (0.8- mu m CMOS). >

The authors propose an HDTV (high-definition television) transmission system design for an SDH (synchronous digital hierarchy)-based STM network. The proposed HDTV coding algorithms are based on subband coding; one uses subband DCT (discrete cosine transform) for HDTV distribution services, while the other uses subband DPCM (differential pulse code modulation) for HDTV contribution services. The network architecture is discussed in regard to providing broadband communication services such as HDTV transmission service upon the introduction of B-ISDN (broadband integrated services digital network) in the early 1990s. The authors also propose a method to compensate for degradation in video transmission systems, i.e., burst errors in STM networks and consecutive cell loss in ATM (asynchronous transfer mode) networks, using random error correcting codes and an interleave structure. An HDTV transmission experimental system using an SDH-based STM network is described. >

Two high-definition television (HDTV) communication systems created for broadband communication networks are discussed. Nationwide HDTV transmission and distribution services and HDTV subscriber distribution services are examined. A network architecture for high-quality HDTV transmission is described. The transmission bit rates of HDTV services, which are the basic factors in constructing the network frame, are considered. Two HDTV coding algorithms, subband discrete cosine transform (DCT) and subband differential pulse-code modulation (DPCM) are described, and their coding bit rates discussed. A synchronous-digital-hierarchy-based synchronous transfer mode network design suitable for the transmission of HDTV signals in broadband communication networks are described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The new demands for high-definition and high resolution video applications are pushing the development of new techniques in the video coding area. Motion estimation (ME) is one of the key elements in video coding standard which eliminates the temporal redundancies between successive frames. In the recent international video coding standards, sub-pixel ME is proposed for its excellent coding performance. DCT (Discrete Cosine Transform) has been widely used for digital signal processing and multimedia applications, especially video codec. In regards to interpolation for motion estimation and compensation, the conventional HEVC employs 8-tap and 4-tap filters for luma and chroma samples respectively. Coefficients in such filters are determined by DCT. This paper presents and implements the DCT-based Quarter-pixel Interpolation filter for motion estimation and compression of HEVC standard using Matlab.

To meet with the different client end devices and network bandwidth transmission requirements, it is necessary to convert the high definition resolution images and videos to standard definition resolution format. A novel approach to convert image resolution with arbitrary ratios in the DCT (Discrete Cosine Transform) domain is proposed, which exploits the relationship of a block and its subblocks with differing size. It can realize arbitrary unequal ratios in the horizontal and vertical direction, respectively. Unlike the present methods, it does not need upsampling- downsampling process. It can perform downsizing directly to the original data and confirms to the standard decoder. The proposed approach is computationally fast and memory efficient and produces visually better images with higher PSNR compared to the spatial methods.

Integer Discrete Cosine Transform (DCT) reduces hardware complexity by eliminating floating point multiplication. Multiplier less multiple constant multiplication (MCM) is used to further optimize integer multiplication by replacing it with shifters and adders. As N-point DCT takes 25% of hardware complexity in high efficiency video coding (HEVC), further optimizing DCT in terms speed and power remains critical. Lately, an alternate real-valued DCT coefficients were proposed which reduced the amount of scaling used in Integer DCT coefficients. It achieved the low dynamic range, high speed and low power at same degree of approximation for DCT coefficients. In this paper, an effort is made to further approximate real-valued DCT coefficients of N-point DCT so that critical path due to MCM is reduced. Proposed approximate real-valued DCT coefficients has relatively good PSNR with optimized hardware compared to existing real-valued DCT coefficients. FPGA implementation of 1D-DCT architecture for 32-point DCT with approximate real-valued coefficients shows the reduction of 35% and 24% in area-delay product and power respectively.

Among various transform coding techniques for image compression the Discrete Cosine Transform (DCT) is considered to be the most effective method and has been widely used in the laboratory as well as in the market, place. DCT is computationally intensive. For video application at 14.3 MHz sample rate, a direct implementation of a 16x16 DCT requires a throughput, rate of approximately half a billion multiplications per second. In order to reduce the cost of hardware implementation, a single chip DCT implementation is highly desirable. In this paper, the implementation of a 16x16 DCT chip using a concurrent architecture will be presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. It uses row-column decomposition to implement the two-dimensional transform. Distributed arithmetic combined with hit-serial and hit-parallel structures is used to implement the required vector inner products concurrently. Several schemes are utilized to reduce the size of required memory. The resultant circuit only uses memory, shift registers, and adders. No multipliers are required. It achieves high speed performance with a very regular and efficient integrated circuit realization. The chip accepts 0-bit input and produces 14-bit DCT coefficients. 12 bits are maintained after the first one-dimensional transform. The circuit has been laid out using a 2-μm CMOS technology with a symbolic design tool MULGA. The core contains approximately 73,000 transistors in an area of 7.2 x 7.0

This paper presents a comparison with the conventional watermarking technique and the novel 5-stage pipelined implementation of DCT/IDCT which is used in digital image watermarking. The most common method of Discrete Cosine Transform (DCT)-based digital image watermarking which is used for image authentication and copyright protection is the transpose method. In this method the 2-Dimensional DCT is obtained by taking two 1-dimensional DCTs in series. The image pixel value is first divided into 8x8 blocks and the row-wise 1D DCT of each block is taken. The transpose of the blocks is then determined and a column-wise 1D DCT is ascertained which gives the 2D DCT of the data. The major advantage of this design is that, unlike the conventional DCT-based watermarking technique, this method uses a 5-stage pipeline which can bring about a speed increase of close to 500% over the conventional method which is naturally a great advantage. This technique has been tested on the standard ‘Lena’ image. Both visible and invisible watermarking is implemented in hardware. The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b. Matlab is used to produce the binary data file which is the input to the 1D DCT module. The hardware implementation is done in Xilinx XC3S4000 FPGA. The results of the comparison are discussed in the concluding sections.

The Discrete Cosine Transform (DCT) is largely used for image and video compression in standards like JPEG and MPEG2. Its simplicity coupled with the fact that it can be computed faster than the Discrete Wavelet Transform (DWT) makes it an attractive option for image and video compression. Consequently a lot of research is in progress to determine novel architectures and algorithms for faster DCT computation having high throughput so that it can even be used for real time applications. For example, when transmitting and receiving videos, which have been compressed using MPEG2, one would like to receive the video, without any buffering delay. In other words, one requires such an architecture, which provides the DCTQ coeffecients at a consistent rate, with very low latency between two coeffecients. As such, a highly parallel and pipelined architecture employing 57 pipeline stages and using fast multipliers and adders is proposed in this work. The proposed DCT Processor is implemented in Spartan 3E FPGA.

Discrete Cosine Transform (DCT) has an important role in image compression. This paper presents a fast 2D-DCT architecture for hardware efficient embedded systems and power limited applications such as Internet of Things (IoT). The proposed design both from a structure point of view and operation reduction point of view has two headed approaches toward the problem of image and video compression. It includes a modified high speed architecture using an extra operational reducing technique. Reduction of operations occurs in two stages while computing 8-point DCT transform of the blocks. Defining the appropriate threshold for comparing DCT domain of two rows of an 8*8 block. Approximating DCT operations column-wise is the additional approach of the paper. The architecture is implemented on Xilinx Vivado 2018.2 with VHDL language on Artix-7 FPGA. 207 MHz clock frequency has achieved.

A new scheme is proposed for the efficient coding of highdefinition television (HDTV) sequences for digital video tape recording. This scheme allows the variable speed playback of recorded material at speeds up to 100 times normal in both the forward and reverse directions. An 8:1 level of compression of the original HDTV data is obtained by exploiting both intraframe and interframe redundancies during the coding process, although the perceptual quality of the reconstructed sequences is uncompromised. To allow the high-quality playback of the recorded data at very high speeds, a hierarchical data structure is employed and the head-positioning capabilities of conventional digital video tape recorders (DVTRs) are exploited to enable the recovery of perceptually vital information at high tape speeds. The performance of the resuIting scheme is examined by simulating the compression and reconstruction of three HDTV sequences at 1, 10, 20, 50, and 100 times normal playback speed.

A 30-ns (600-MOPS) image processor is described. The 200 K-transistor chip has been fabricated in a 1.2-mm CMOS. A reconfigurable pipeline architecture with an array of nine multiplier/accumulators (MAC) is implemented by interchanging its pipelined data paths. This allows it to perform both matrix products and convolutions, systolically, for the discrete cosine transform (DCT) and transversal filters at HDTV rate. 512 by 512-pixel image data can be computed in less than 7.9 ms with sufficient resolution

A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD) representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coefficient matrix is used with CSE to further decrease the number of arithmetic operations. This architecture needs a single-port memory to feed the inputs instead of multiport memory, which leads to reduction of the hardware cost and area. From the analysis of experimental results and performance comparisons, it is observed that the proposed scheme uses minimum logic utilizing mere 340 slices and 22 adders. Moreover, this design meets the real time constraints of different video/image coders and peak-signal-to-noise-ratio (PSNR) requirements. Furthermore, the proposed technique has significant advantages over recent well-known methods along with accuracy in terms of power reduction, silicon area usage, and maximum operating frequency by 41%, 15%, and 15%, respectively.