Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform

Allocation problem has always been one of the fundamental issues of building the applications in real-time computing systems. For real-time applications, the allocation problem should directly address the issues of task and communication scheduling. In this context, the allocation of tasks has to fully utilize the available processors and the scheduling of tasks has to meet the specified timing constraints. Clearly, the execution of tasks under the allocation and schedule has to satisfy the precedence, resources, and other synchronization constraints among them. Recently, the timing requirements of the real-time systems emerge that the relative timing constraints are imposed on the consecutive executions of each task and the inter-task temporal relationships are specified across task periods. In this paper we consider the allocation and scheduling problem of the periodic tasks with such timing requirements. Given a set of periodic tasks, we consider the least common multiple (LCM) of the task periods. Each task is extended to several instances within the LCM. The scheduling window for each task instance is derived to satisfy the timing constraints. We develop a simulated annealing algorithm as the overall control algorithm. An example problem of the sanitized version of the Boeing 777 Aircraft Information Management System is solved by the algorithm. Experimental results show that the algorithm solves the problem in a reasonable time complexity.

Cloud computing and big data: Technologies and applications

<span>The distributed fog node network and variable workloads make task distribution difficult in fog computing. Optimizing computing resources for dynamic workloads with heuristic and metaheuristic algorithms has shown potential. To address changing workloads, these algorithms enable real-time decision-making. This systematic review examines heuristic, meta-heuristic, and real-time dynamic job scheduling strategies in fog computing. Static methods like heuristic and meta-heuristic algorithms can help modify dynamic task scheduling in fog computing situations. This paper covers a current study area that stresses real-time approaches, meta-heuristics, and fog computing environments' dynamic nature. It also helps build reliable and scalable fog computing systems by spotting dynamic task scheduling trends, patterns, and issues. This study summarizes and analyzes the latest fog computing research on task-scheduling algorithms and their pros and cons to adequately address their issues. Fog computing task scheduling strategies are detailed and classified using a technical taxonomy. This work promises to improve system performance, resource utilization, and fog computing settings. The work also identifies fog computing job scheduling innovations and improvements. It reveals the strengths and weaknesses of present techniques, paving the way for fog computing research to address unresolved difficulties and anticipate future challenges.</span>

Heterogeneous Distributed Computing (HDC) system consists of Workstations (WSs) and Personal Computers (PCs). In HDC system, each WS/PC may have different processor and performance. In order to take advantage of this diversity of processing power of a system, an effective task partitioning, scheduling, and load balancing are needed to get the optimum performance. This paper examines the effectiveness of task partitioning and scheduling strategies for image (raytracing) processing application on HDC system. The static and dynamic/Run-time Task Scheduling (RTS) strategies are shown inadequate for balancing the load of HDC system. Two adaptive tasks scheduling strategies are proposed for HDC image computing system. These adaptive strategies are: i) Master Initiate Sub-task size (MIS) strategy (based on centralized resources management approach), and ii) Worker Initiated Sub-task size (WIS) strategy (based on semi-decentralized resources management approach). The measured results show that the adaptive (MIS & WIS) strategies dramatically improve the performance of HDC raytracing system and remedy the defects of static and RTS strategies. Performances of the all investigated strategies are evaluated on manager/master and workers model of HDC system. In performance comparisons of MIS and WIS strategies, the WIS strategy shows a slightly better speedup and scalability over MIS strategy.

Traditional real-time task scheduling strategies focus on solely on the CPU, and do not take in account memory access and cache effects. In this paper we propose real-time parallel scheduling (PRTTS) strategy on multicore platforms. Each task is represented as a directed acyclic graph (DAG). Tasks priorities are assigned according to task periods (rate monotonic, RM). In PRTTS scheduling strategy priorities of tasks which access memory are promoted over priorities of tasks not accessing memory. Tasks which read/write data in cache dynamically have their priority increased above all tasks. The results of simulation experiment show that proposed scheduling strategy offers better performance in terms of core utilization and schedulability rate of tasks.

Multicore platforms are increasingly used in real-time embedded applications. In the development of such applications, an efficient use of RAM memory is as important as the effective scheduling of software tasks. Preemption Threshold Scheduling is a well-known technique for controlling the degree of preemption, possibly improving system schedulability, and allowing savings in stack space. In this paper, we target at the optimal mapping of tasks to cores and the assignment of the scheduling parameters for systems scheduled with preemption thresholds. We formulate the optimization problems using Mixed Integer Linear Programming framework, and propose an efficient heuristic as an alternative. We demonstrate the efficiency and quality of both approaches with extensive experiments using random systems as well as two industrial case studies.

Task mapping is an important issue in MPSoC design. Most recent mapping algorithms perform them at design time, an approach known as static mapping. Nonetheless, applications running in MPSoCs may execute a varying number of simultaneous tasks. In some cases, applications may be defined only after system design, enforcing a scenario that requires the use of dynamic task mapping. Static mappings have as main advantage the global view of the system, while dynamic mappings normally provide a local view, which considers only the neighborhood of the mapping task. This work aims to evaluate the pros and cons of static and dynamic mapping solutions. Due to the global system view, it is expected that static mapping algorithms achieve superior performance (w.r.t. latency, congestion, energy consumption). As dynamic scenarios are a trend in present MPSoC designs, the cost of dynamic mapping algorithms must be known, and directions to improve the quality of such algorithms should be provided without increasing execution time. This quantitative comparison between static and dynamic mapping algorithms is the main contribution of this work.

Summary form only given. Modern programming languages are provided with a mechanism for automatic memory management called garbage collection. A lot of researches had been introduced in this area. On the other hand, some problems existed when applying such languages to the real-time applications. Among these problems, there was the threat of predictability and schedulability of hard real-time tasks. As a solution, different concurrent garbage collection scheduling strategies had been proposed. Unfortunately, these concurrent garbage collectors suffered from redundant usage of system memory. A latter algorithm that minimizes the worst-case system memory requirement with the schedulability of tasks not jeopardized is the deferrable server based garbage collector scheduling strategy. The deferrable server based garbage collection had been proved to surpass all other garbage collection scheduling strategies in minimizing system memory requirements under the worst-case conditions. In this paper, the performance of the deferrable server based garbage collector is explored under the actual real-time working environment. It also investigates the selection of thresholds to further reduce the memory requirement by using higher capacities of the deferrable server task. The simulation results demonstrate that the deferrable sever based garbage collector achieves better performance under actual real-time environment than other garbage collection algorithms. It also shows that using higher values for the server capacities can lead to better memory usage if a proper value of threshold is chosen.

Heterogeneous systems with multiple different compute devices have come into common use recently, and the heterogeneity of the compute device is mainly reflected in three aspects: hardware architecture, instruction set architecture, and processing capability. Heterogeneous CPU-accelerator systems have attracted increasing attention especially. To make full use of multiple CPUs and accelerators to execute data-parallel applications, programmers may need to manually map computation and data to all available compute devices, which is tedious, error-prone, and difficult. Especially for some data-parallel applications, the inter-device communication could easily become the performance bottleneck of multi-device co-execution. Therefore, firstly, a runtime system is designed for supporting heterogeneous cooperative execution (HCE) of data-parallel applications, which can help programmers to automatically and efficiently map computation and data to multiple compute devices. Secondly, an incremental data transfer method is designed to avoid redundant data transfers between devices, and a three-way overlapping communication optimization method based on software pipelining is designed to effectively hide the inter-device communication overhead. Based on our previously proposed feedback-based dynamic and elastic task scheduling (FDETS) scheme and asynchronous-based dynamic and elastic task scheduling (ADETS) scheme, the modified FDETS that supports incremental data transfer and the modified ADETS that supports three-way overlapping communication optimization are proposed, which not only can effectively partition and balance the workload among multiple compute devices but also can significantly reduce data transfer overhead between devices. Thirdly, a prototype of the proposed runtime system is implemented, which provides a set of runtime APIs for task scheduling, device management, memory management, and transfer optimization. Our experimental results show that the communication overhead between devices is greatly reduced using the proposed inter-device communication optimization methods and the multi-device co-execution significantly outperforms the best single-device execution.

The scheduling of tasks with deadlines on clusters is a key issue for offering quality-of-service (QoS) assurance. A critical challenge in real-time task scheduling is to handle various types of applications. This paper investigates the scheduling problem for processing a set of tasks comprising both divisible and indivisible real-time tasks on cluster systems. Indivisible tasks are characterized by the property that they need to be processed on their entirety on a single processor while divisible tasks can be distributed across several processing nodes by exploiting the underlying data parallelism. We propose a dynamic (on-line) real-time scheduling algorithm referred to as Hybrid Loads Push-Pull Scheduling (HLPPS) algorithm for handling a set of tasks comprising both divisible and indivisible real-time tasks on cluster systems. HLPPS is shown to efficiently exploit the parallelism in divisible tasks without undermining the schedulability of indivisible tasks and thereby optimize the overall performance. We consider two distinct network platforms - tightly coupled and loosely coupled clusters in designing the strategy. We conduct extensive performance evaluation studies to quantify the performance of the proposed algorithm under a variety of scenarios.

Modern Advanced Driver-Assistance Systems (ADAS) combine critical real-time and non-critical best-effort tasks and messages onto an integrated multi-core multi-SoC hardware platform. The real-time safety-critical software tasks have complex interdependencies in the form of end-to-end latency chains featuring, e.g., sensing, processing/sensor fusion, and actuating. The underlying real-time operating systems running on top of the multi-core platform use static cyclic scheduling for the software tasks, while the communication backbone is either realized through PCIe or Time-Sensitive Networking (TSN). In this paper, we address the problem of configuring ADAS platforms for automotive applications, which means deciding the mapping of tasks to processing cores and the scheduling of tasks and messages. Time-critical messages are transmitted in a scheduled manner via the timed-gate mechanism described in IEEE 802.1Qbv according to the pre-computed Gate Control List (GCL) schedule. We study the computation of the assignment of tasks to the available platform CPUs/cores, the static schedule tables for the real-time tasks, as well as the GCLs, such that task and message deadlines, as well as end-to-end task chain latencies, are satisfied. This is an intractable combinatorial optimization problem. As the ADAS platforms and applications become increasingly complex, such problems cannot be optimally solved and require problem-specific heuristics or metaheuristics to determine good quality feasible solutions in a reasonable time. We propose two metaheuristic solutions, a Genetic Algorithm (GA) and one based on Simulated Annealing (SA), both creating static schedule tables for tasks by simulating Earliest Deadline First (EDF) dispatching with different task deadlines and offsets. Furthermore, we use a List Scheduling-based heuristic to create the GCLs in platforms featuring a TSN backbone. We evaluate the proposed solution with real-world and synthetic test cases scaled to fit the future requirements of ADAS systems. The results show that our heuristic strategy can find correct solutions that meet the complex timing and dependency constraints at a higher rate than the related work approaches, i.e., the jitter constraints are satisfied in over 6 times more cases, and the task chain constraints are satisfied in 41% more cases on average. Our method scales well with the growing trend of ADAS platforms.

Workload allocation in embedded multicore platforms is an increasing challenging issue due to heterogeneity of components and their parallelism. Additionally, the impact of process variations in current and next generation technology nodes is becoming relevant and cannot be compensated at the device or architectural level. Intra-die process variations raising at the core level and platform level makes parallel multicore platforms intrinsically heterogeneous, because the various cores are clocked at different operational frequencies. Power consumption becomes heterogeneous too, both considering dynamic and leakage consumption. In this context, to fully exploit the computational capability of the platform parallelism, variability aware task allocation strategies must be adopted. Despite the consistent research performed to design variability-aware task allocation policies, little effort has been devoted make available to programmers a software toolchain enabling the exploitation of these policies. Such toolchain need to exploit fabrication-level information about core clock speed and power consumption. In this work, we address to present a methodology and the associated toolchain to program in presence of process variability, integrating power and performance variability information in all the steps of the toolchain. To this purpose, the proposed approach is vertically integrated, from high level modelling down to runtime management. Variability information is introduced through a XML configuration file that is exploited by toolchain components to make the appropriate runtime allocation decision. We demonstrate the proposed toolchain using state of art variability-aware task allocation policies on two multicore platforms: i) The MIPS-based GENEPY simulator with 4 and 8 parallel homogeneous cores and ii) The Tegra2-based Zynq platform, where the on-board FPGA has been used to map 10 microblaze slave cores. Experiments show that the proposed toolchain supports the integration of variability awareness in a simple yet effective programming environment.

Multicore processors are increasingly adopted in resource-constrained real-time embedded applications. In the development of such applications, efficient use of RAM memory is as important as the effective scheduling of software tasks. Preemption Threshold Scheduling (PTS) is a well-known technique for controlling the degree of preemption, possibly improving system schedulability, and to reduce system stack usage. In this paper, we consider partitioned multi-processor scheduling on a multicore processor with either Fixed-Priority or Earliest Deadline First scheduling algorithms with PTS and address the design optimization problem of mapping tasks to processor cores and assignment of task priorities and preemption thresholds with the optimization objective of minimizing system stack usage. We present both optimal solution techniques based on Mixed Integer Linear Programming and efficient heuristic algorithms that can achieve high-quality results. We perform extensive performance evaluations using both synthetic tasksets and industrial case studies.

In this paper, we tackle the problem of minimizing the power consumption of multiple-processors-core system using multiple variable supply voltages. Given a set of tasks and their dependency, and a set of target processors, we propose a method which carries out task allocation on processors, task scheduling and voltage assignment for each task concurrently. The problem is formulated as a mixed integer nonlinear programming (MINLP) optimization problem and optimal solution can be obtained. The MINLP problem is solved by the branch and bound algorithm. To reduce the run time, we propose two modifications of the formulation. Experimental results show that significant power reduction is achieved using the proposed approach.

In multi-core systems, main memory is a major shared resource among processor cores. A task running on one core can be delayed by other tasks running simultaneously on other cores due to interference in the shared main memory system. Such memory interference delay can be large and highly variable, thereby posing a significant challenge for the design of predictable real-time systems. In this paper, we present techniques to reduce this interference and provide an upper bound on the worst-case interference on a multi-core platform that uses a commercial-off-the-shelf (COTS) DRAM system. We explicitly model the major resources in the DRAM system, including banks, buses, and the memory controller. By considering their timing characteristics, we analyze the worst-case memory interference delay imposed on a task by other tasks running in parallel. We find that memory interference can be significantly reduced by (i) partitioning DRAM banks, and (ii) co-locating memory-intensive tasks on the same processing core. Based on these observations, we develop a memory interference-aware task allocation algorithm for reducing memory interference. We evaluate our approach on a COTS-based multi-core platform running Linux/RK. Experimental results show that the predictions made by our approach are close to the measured worst-case interference under workloads with both high and low memory contention. In addition, our memory interference-aware task allocation algorithm provides a significant improvement in task schedulability over previous work, with as much as 96 % more tasksets being schedulable.