Deadline constrained cyclic scheduling on pipelined dedicated processors considering multiprocessor tasks and changeover times

Solving Integer Linear Programming (ILP) models generally lies in the category of NP-hard problems. Therefore, as the size of ILP models grows, the efficiency of exact algorithms for solving the models reduced significantly and for large models it is not possible to have the result. Genetic Algorithm (GA) is a metaheuristic method capable of adjusting and redesigning parameters and operations according to the characteristics of ILP models. Still GA has huge search space for large models and parallelization is a suitable technique to tackle this problem. This paper presents a scalable parallel GA to solve large ILP models derived from behavioral synthesis of digital circuits. We show that although models have non-binary variables, only binary variables are sufficient for coding chromosomes. We also use ”unknown” values for some genes to decrease the likelihood of inconsistency in the encoded constraints. Our experiments verify the efficiency and scalability of the proposed algorithm on multicore platforms. The proposed method outperforms IBM ILOG CPLEX 12.6 and MI-LXPM algorithm where the ILP models include 550 to 2258 int / binary decision variables. Also, the results indicate that the saturation point of using parallel processing elements for solving the large ILP models is at least 60.

A branch and bound algorithm for a single-machine scheduling problem with positive and negative time-lags

An Optimal Cross-Layer Scheduling for Periodic WSN Applications

A new Field Programmable Gate Array (FPGA) architecture is described. This architecture includes a number of novel features not found in currently available FPGAs. It is believed to offer a significantly improved logic density in some common applications.This paper describes the development of the FPGA and looks at the mapping onto it of some interesting application circuit elements. The design is discussed in approximately chronological order which allows us to explain other options which were considered and rejected during the development process.KeywordsField Programmable Gate ArrayMemory ArrayField Programmable Gate Array ImplementationCrossbar SwitchLarge GateThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

To meet the operational requirements and to ensure safe operations, train units of a passenger railway operator require inspection and/or cleaning at the maintenance depots after running a specified mileage or time period. Accordingly, these inspection and cleaning activities are called depot services. In this paper, we propose an integer linear programming (ILP) model for the integrated optimization problem of depot service scheduling, train parking, and train routing. Both short trains (8 marshaling) and long trains (16 marshaling) are considered in the ILP model which is a combinational optimization problem in the dead-end tracks scenario. Moreover, a real-world case study of the Shanghai South Depot, China is carried out to further examine the effectiveness and efficiency of the proposed methodology. Computational results indicate that our method is able to generate optimized shunting plans for the linearized INLP within reasonable solution time for real-life applications, outperforming the manual method in terms of the solution quality and the computation speed.

This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To facilitate the design process we present an optimal scheduling algorithm using a very universal framework, where tasks are constrained by precedence delays and relative deadlines. The precedence relations are given by an oriented graph, where tasks are represented by nodes. Edges in the graph are related either to the minimum time or to the maximum time elapsed between the start times of the tasks. This framework is used to model the runtime dynamic reconfiguration, synchronization with an on-chip processor and simultaneous availability of arithmetic units and SRAM memory. The NP-hard problem of finding an optimal schedule satisfying the timing and resource constraints while minimizing the makespan C max , is solved using two approaches. The first one is based on Integer Linear Programming and the second one is implemented as a Branch and Bound algorithm. Experimental results show the efficiency comparison of the ILP and Branch and Bound solutions.

This paper is motivated by existing architectures of field programmable gate arrays (FPGAs). To facilitate the design process we present an optimal scheduling algorithm using a very universal framework, where tasks are constrained by precedence delays and relative deadlines. The precedence relations are given by an oriented graph, where tasks are represented by nodes. Edges in the graph are related either to the minimum time or to the maximum time elapsed between the start times of the tasks. This framework is used to model the runtime dynamic reconfiguration, synchronization with an on-chip processor and simultaneous availability of arithmetic units and SRAM memory. The NP-hard problem of finding an optimal schedule satisfying the timing and resource constraints while minimizing the makespan C max , is solved using two approaches. The first one is based on Integer Linear Programming and the second one is implemented as a Branch and Bound algorithm. Experimental results show the efficiency comparison of the ILP and Branch and Bound solutions.

This paper focus on the routing, modulation level and spectrum allocation (RMLSA) problem in the next generation datacentre networks, which own the advantages of both Elastic Optical Networks (EON) and Software Defined Networking (SDN). We proposes an Integer Linear Programming (ILP) model for this problem. Simulation results show the ILP model achieves an outstanding load balancing performance.

In this paper, we propose an integer linear programming (ILP) model for static elevator operation problems. The proposed model is based on hall- and car-calls which correspond to pickup and delivery requests in pickup-and-delivery problems (PDPs), thus is similar to ILP models for PDPs. The primary difference between those models and the proposed model is the prevention of the reverse run, which means that an elevator with a passenger is moved to the direction opposite to that of the passenger. In computer illustrations, the proposed model is roughly investigated by being compared with a trip-based ILP model which has been proposed by the authors.

This paper addresses the problem of minimizing spectrum usage for shared-path protection with joint failure probability constraint in flexible bandwidth optical networks. To achieve this goal, we propose an integer linear programming (ILP) model for shared-path protection and a heuristic spectrum-aware shared protection (SASP) algorithm that considers joint failure probability. Simulation results show that the ILP model minimizes the total usage of frequency slots and average hops, but leads to high average joint failure probability. Moreover, the SASP algorithm achieves better trade-off between total usage of frequency slots and average joint failure probability compared to the ILP model and a conventional shared-path protection (CSPP) algorithm. As expected, in a 14-nodes network, the SASP algorithm performs better with respect to total spectrum usage and average hops, but results in much larger average joint failure probability compared to the CSPP algorithm.

Production Lot Sizes on a Single Imperfect Machine: FPTAS vs ILP models

In this work, we propose an integer linear programming (ILP) model to schedule a set of weakly-hard real-time tasks on a heterogeneous multiprocessor system to minimize energy consumption with the predictable performance. The ILP model provides an optimal solution in terms of energy consumption by selecting the appropriate frequency for each task with (m,k) weakly-hard deadline constraint.

Efficient and scalable provisioning of always-on multicast streaming services

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two physical limitations: (1) The massive usage of routing multiplexers causes delay and power overheads as compared to ASICs. To reduce their power consumption, FPGAs have to operate at low supply voltage but sacrifice performance because the transistors drive degrade when working voltage decreases. (2) Using volatile memory technology forces FPGAs to lose configurations when powered off and to be reconfigured at each power Resistive Random Access Memories (RRAMs) have strong potentials in overcoming the physical limitations of conventional FPGAs. First of all, RRAMs grant FPGAs non-volatility, enabling FPGAs to be Normally powered off, Instantly powered on. Second, by combining functionality of memory and pass-gate logic in one unique device, RRAMs can greatly reduce area and delay of routing elements. Third, when RRAMs are embedded into datpaths, the performance of circuits can be independent from their working voltage, beyond the limitations of CMOS circuits. However, researches and development of RRAM-based FPGAs are in their infancy. Most of area and performance predictions were achieved without solid circuit-level simulations and sophisticated Computer Aided Design (CAD) tools, causing the predicted improvements to be less convincing. In this thesis,we present high-performance and low-power RRAM-based FPGAs fromtransistorlevel circuit designs to architecture-level optimizations and CAD tools, using theoretical analysis, industrial electrical simulators and novel CAD tools. We believe that this is the first systematic study in the field, covering: From a circuit design perspective, we propose efficient RRAM-based programming circuits and routing multiplexers through both theoretical analysis and electrical simulations. The proposed 4T(ransitor)1R(RAM) programming structure demonstrates significant improvements in programming current, when compared to most popular 2T1R programming structure. 4T1R-based routingmultiplexer designs are proposed by considering various physical design parasitics, such as intrinsic capacitance of RRAMs and wells doping organization. The proposed 4T1R-based multiplexers outperformbest CMOS implementations significantly in area, delay and power at both nominal and near-Vt regime. From a CAD perspective, we develop a generic FPGA architecture exploration tool, FPGASPICE, modeling a full FPGA fabric with SPICE and Verilog netlists. FPGA-SPICE provides different levels of testbenches and techniques to split large SPICE netlists, in order to obtain better trade-off between simulation time and accuracy. FPGA-SPICE can capture area and power characteristics of SRAM-based and RRAM-based FPGAs more accurately than the currently best analyticalmodels. From an architecture perspective, we propose architecture-level optimizations for RRAMbased FPGAs and quantify their minimumrequirements for RRAM devices. Compared to the best SRAM-based FPGAs, an optimized RRAM-based FPGA architecture brings significant reduction in area, delay and power respectively. In particular, RRAM-based FPGAs operating in the near-Vt regime demonstrate a 5x power improvement without delay overhead as compared to optimized SRAM-based FPGA operating at nominal working voltage.

We present new integer linear programming (ILP) models for NP-hard optimisation problems in instances of the Stable Marriage problem with Ties and Incomplete lists (SMTI) and its many-to-one generalisation, the Hospitals/Residents problem with Ties (HRT). These models can be used to efficiently solve these optimisation problems when applied to (i) instances derived from real-world applications, and (ii) larger instances that are randomly-generated. In the case of SMTI, we consider instances arising from the pairing of children with adoptive families, where preferences are obtained from a quality measure of each possible pairing of child to family. In this case, we seek a maximum weight stable matching. We present new algorithms for preprocessing instances of SMTI with ties on both sides, as well as new ILP models. Algorithms based on existing state-of-the-art models only solve 6 of our 22 real-world instances within an hour per instance, and our new models incorporating dummy variables and constraint merging, together with preprocessing and a warm start, solve all 22 instances within a mean runtime of a minute. For HRT, we consider instances derived from the problem of assigning junior doctors to foundation posts in Scottish hospitals. Here, we seek a maximum size stable matching. We show how to extend our models for SMTI to HRT and reduce the average running time for real-world HRT instances by two orders of magnitude. We also show that our models outperform by a wide margin all known state-of-the-art models on larger randomly-generated instances of SMTI and HRT.