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Decision feedback equalization with quarter-rate clock timing for high-speed backplane data communications

  • Jan 1, 2005
  • Miao Li +3 more
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Abstract

Decision feedback equalization (DFE) is a popular technique to counteract inter-symbol interference (ISI) in high-speed backplane data communications. Quarter-rate clock timing for DFE circuit design is proposed to alleviate the speed requirement of the clock timing. A receiver implemented in 0.18-/spl mu/m CMOS technology demonstrates 6.25Gb/s and 8Gb/s operation over a 34" FR4 backplane.

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