Decoupled technique for the simulation of PWM switching regulators using second-order-output extrapolations

Voltage source inverter (VSI) is one of the most common types of power converters, which is used in various industries. The energy efficiency indicators of the AVI depend not only on the IGBT or MOSFET-based transistors used in the AVI element, but also on the chosen modulation algorithm.The most commonly used in VSI is pulse width modulation (PWM) and single modulation. The advantage of PWM prior to single modulation is the ability to control the amplitude of the first harmonic of the output voltage and, accordingly, the current required both for scalar and vector control of an asynchronous electric drive.At the same time, the disadvantage of PWM is the need for a higher switching frequency of power switches, which results in higher dynamic losses. In addition, in the PWM mode, VSI at the same load parameters has a smaller amplitude of the first harmonic of the output voltage, and hence less output power.The article proposes the use the mode of overmodulation algorithm in the pulse-width modulation (PWM) mode for a three-level autonomous voltage inverter, which is relatively classical PWM with a modulation factor equal to one, justified and allows to increase the control range of the output power of the VSI, to reduce the dynamic losses in the power switches, to improve the sinusoidal output current, as well as reduce the ripple factor of the input current. Given the dependence of the energy indicators of the VSI on the modulation factor in the mode of overmodulation.In the specialized MelcoSim program from Mitsubishi, the calculation of static and dynamic losses in the power switches of an autonomous voltage inverter in the mode of overmodulation was performed. The dependences of the output power on the modulation coefficient, the dependence of the amplitude of the first harmonic of the output current on the modulation coefficient, the dependence of the coefficient of harmonic distortion of the output voltage on the modulation coefficient, the dependence of the harmonic distortion factor of the output current on the modulation coefficient, and the dependence of the losses in the power switches on the modulation coefficient.

PurposeThis paper aims to propose Hidden Converter (H-Converter) combined with dual port 3Ø inverter for energy storage application to produce wide range of voltage. Some of the application required wide range of voltages, but problem from E-chopper is either boost or buck mode of operations, both modes are not possible. To overcome this drawback, H-Converter is combined with dual port 3Ø inverter controlled by carrier-based pulse width modulation (CB-PWM) technique is added with zero sequence injection.Design/methodology/approachHidden converter is a bidirectional DC-DC chopper used to convert fixed DC to variable DC and vice versa in both buck and boost modes of operations. Dual port inverter is combined with hidden DC-DC converter can produce wide range of voltages.FindingsThe bidirectional DC-AC converter requires less power for processing and consumes less power losses by using modest carrier built- pulse width modulation scheme through proposed zero structure addition.Originality/valueBy using this proposed strategy H-Converter can produce wide range of voltage in both the sides and mostly power is processed in the 3Ø inverter with a one stage conversion with less power loss. As a result, with one stage power conversion has more efficiency because of less power loss. This proposed converter has designed by analysis, and the real time result is tested in an experiment.

This paper discusses the design and simulation of pulse width modulated based circuit for induction melting application. This high frequency inverter topology have the practical advantages of energy saving, clean environment, high output power due to low switching losses, less electromagnetic noise and low total harmonic distortion. This two stage power converter has single phase full bridge rectifier, DC filter, zero voltage switching pulse width modulation controlled high frequency inverter. In this work, the steady state operation and control strategy of pulse width modulated high frequency inverter is analyzed. In order to achieve energy efficiency switching losses are reduced by operating the inverter above resonance frequency. Input side supply harmonics is also reduced using EMI filter. The simulation of the designed high frequency power supply is carried out at a frequency of 20 kHz using MATLAB simulink tool. Simulation results proof the energy saving due to reduction in switching losses of the presented control strategy and reduction in harmonic distortion of the presented power supply for induction heating load.

Integrated power management (PM) in a system-on-a-chip (SoC) includes a high-efficiency DC-DC switching regulator (SWR) for a high conversion ratio and multiple cascaded digital-low-dropout (DLDO) regulators for post regulation to different functional blocks. Efficient power-saving modes in the SWRs improve the light-load efficiency effectively, e.g. burst mode, skip mode, pulse frequency mode (PFM), and diode emulation mode (DEM) in the constant on-time (COT). Unfortunately, a cascaded DLDO consumes significant power to suppress a large voltage ripple DV SWR from the SWR, even using recent DLDO techniques [1-6], illustrated on the left of Fig. 18.8.1. Overall, the light-load efficiency of the PM seriously decreases. A DLDo with barrel-shifter-based control [1] induces large voltage ripple due to the limiting cycle oscillation (LCO), and the DLDO with freeze mode [2] for power reduction is exposed to large voltage ripples from the SWRs (in power saving modes). The large voltage ripples result in the DLDO frequently switching between the normal and freeze modes and consuming power. The recursive all-digital LDO (RLDO) [3] abruptly changes its control code Q[6:0] due to oscillations between hybrid proportional-derivative successive-approximation recursive (PD-SAR) and pulse width modulation (PWM) duty control, while aV SWR is larger than the pre-defined hysteretic window. In power saving modes, the obvious disadvantage is that state-of-the-art DLDO designs cause extra switching loss and induce large output voltage ripple aV OUT due to large aV SWR . Thus, this paper proposes a DLDO employing a burst mode technique (BMT) to reduce the DV OUT , thereby enhancing the overall light-load efficiency corresponding to the power saving modes in SWRs. The proposed non-linear switch control (NLSC) technique reduces both the number of on/off power switches and varies the switching frequency corresponding to the aV SWR . Moreover, the proposed transient enhance (TE) technique improves transient performance when the DLDO leaves burst mode.

Pulse width modulation (PWM) is widely used in different applications. PWM transforms the information in the amplitude of a bounded input signal into the pulse width output signal without suffering from quantization noise. The frequency of the output signal is usually constant. In this paper, the new PWM system with frequency changing (PWMFM) is described. In such PWMFM the pulse width and also the carrier frequency are changed. Therefore, two independent pieces of information can be simultaneously transmitted over one channel; hence PWM and frequency modulation (FM) are simultaneously used. But such system needs 2 demodulators, one for PWM and the second for FM. PWMFM can be used in the following applications: LED light intensity control via PWM and several LED block switching by FM PWMFM is highly useful in motor speed control applications by PWM and direction of rotation with FM. PWMFM can be used also in a class-D audio amplifier for power control, e.g. coarse by means of FM and fine by PWM. PWMFM can be used for the simultaneous transmission of two independent information between all, mutual combinations of analog and digital circuits. The analog and digital circuits for modulation and demodulation of PWMF signal are described and measuring results are presented in this work.

Synchronous pulse width modulation (PWM) switching regulator is suitable for high-power applications because of its high conversion efficiency as compared with a linear regulator. A synchronous PWM chip integrating the control, output adjustment, output monitoring and protection functions of a switching regulator is designed for the power supply of high-performance CPUs. This chip is fabricated with a 1.7 /spl mu/m BiCMOS process successfully and a synchronous switching power system is established. The test result shows this system has high efficiency, high precision, fast transient response and small start-up overshoot.

The leakage current in grid-interface converter systems presents a considerable issue in regard to safety and efficiency. The full-bridge inverter is a well-accepted topology in single-phase power conversion applications. The high-frequency pulsewidth modulation (PWM) modulation schemes are normally applied to the full-bridge topology for smaller ac filter size, which, however, generates a high-frequency dc-side leakage current, resulting in an enormous negative impact on dc components, such as photovoltaic panels and energy storage elements. In this paper, a modified full-bridge inverter topology to reduce the dc-side leakage current as well as to mitigate the ac-side common-mode electromagnetic interference noise is presented. Several considerations are discussed, such as the PWM modulation and filter design. Compared to the other existing methods, the proposed solution provides a reliable performance for bidirectional operation, minimum additional components, low cost, and a simple design process.

DC-DC pulse-width modulated (PWM) converters are nonlinear systems that require control circuits to obtain the desired output voltage. These control circuits are often designed using linearized models of the converters, so modeling is a relevant topic for the design of performing closed-loop converters. In this paper, the nonlinear nature of DC-DC PWM converters operated under continuous conduction mode (CCM) is considered. It is first shown how the exact periodic solutions can be analytically computed for the nonlinear converter model in the high-frequency steady-state operating condition. Also, a nonlinear variation model, which characterizes the closed-loop dynamics, induced by perturbations of the steady state, is provided. The nonlinear models and the analytical periodic solutions are implemented in MATLAB and SIMULINK and applied to a boost converter subject to parasitic components. In particular, the behavior to step changes in duty cycle, input voltage, and load resistance are compared with the results obtained using small-signal circuit averaging techniques.

Currently the market of three-phase standalone voltage inverters and frequency converters, which are to be used in alternating current drive and power supply, develops together with systems of control and voltage support. In connection with this, research and development of three phase stand-alone voltage inverters, that are used in control of alternating current systems, is relevant to a great degree. One of the main stages of developing the stand-alone voltage inverter is designing the control system. Any kind of control of the power converter ultimately comes down to controlling the open state time of power transistor in relation to period of its work. This method of control is referred to as the pulse width modulation. In this study the method of vector-based pulse width modulation is considered for the case of the frequency converters control system. The core of the vector pulse width modulation is about refusing from the simultaneous turning on/off all the switches during the switching period (if pulse width modulation is sine-based) in favor to switching between several pre-selected conditions of the inverter, each of which is corresponding to some spatial position of the vector. The analysis of the frequency converters operation, based on the vector pulse width modulation, is considered. The regularities describing electromagnetic transients in the frequency converters are discovered. The mathematical and computer models of the frequency converters based on the vector pulse width modulation are developed.

This paper presents a novel approach to compensate the voltage error due to switching dead times in voltage-fed inverters using a field-programmable gate array (FPGA) and current oversampling. The FPGA controls an analog-to-digital (AD) converter which operates at a high conversion rate and processes numerous current samples taken at equidistant time steps within each pulse width modulation (PWM) period. The FPGA also generates the inverter's PWM modulation. As phase currents at an inductive load can be approximated by piecewise linear time functions during each switching state of the inverter, the FPGA interpolates the current slopes using a linear least mean squares regression. Based on this regression, a predictor structure in the FPGA predicts the phase current right at the beginning of the switching dead time. The predictor structure can be computed almost instantaneously due to parallel data processing. Based on the estimated phase current, the FPGA uses a lookup table, depending on current and DC link voltage, to correct an upcoming switching instant in order to compensate for the dead-time effect. Depending on current polarity and magnitude, the lookup table stores the respective compensation times for the upcoming switching instants. The lookup table is the result of an offline commissioning process.

Presently most of the countries are looking towards the renewable energy systems like solar PV systems to overcome the drawbacks of conventional energy systems. This paper mainly deals with the power conditioning system controlled with FPGA for solar PV fed systems. A power conditioning system is proposed here for PV System comprising of 2 stage power conversion using FPGA. The first stage converts the variable DC voltage obtained from solar PV module/array into fixed DC using Boost converter which operates in voltage mode control technique. In the second stage of power conversion, the output of the first stage is fed to 3-phase, 3-level Diode clamped Inverter and the same is controlled by level shifted Sinusoidal pulse width modulation technique to convert fixed DC into 3 phase AC to drive 3 phase AC loads effectively.

Standard pulsewidth modulation (PWM) schemes for modular multilevel converters (MMC) have neglected deviations of the module voltages from the mean module voltage of an MMC arm as well as the dynamic change in the module voltages since their last measurement and during the switching period. This induces an output voltage error. Large output voltage errors disturb the higher level closed-loop control of the MMC, such that control targets cannot be met anymore. The output voltage error can be reduced using advanced PWM methods that predict and include the dynamic change of the individual module voltages during a switching period in the calculations for the duty cycle. This paper shows measurement results obtained from an experimental medium-voltage prototype, proving that advanced methods lead to much lower output voltage errors than the standard methods, but cannot fulfill the expectations raised by the simulations documented in the literature. In order to overcome the limitations of the old method, a new method that includes the semiconductor voltage drop and parasitic resistances is introduced and evaluated with measurements in this paper. Furthermore, simulation results showing the influence of the considered modulation methods on the closed-loop current control performance are presented.

High brightness white LED has attracted a lot of attention from both industry and academia for its high efficacy, simple to drive, environmentally friendly, and long lifespan. It becomes possible applications to replace the incandescent bulbs, halogen bulbs, and even compact fluorescent light bulbs in residential, industry and commercial lighting. Offline application of this new lighting source requires both tight LED current regulation and high power factor as well. We proposed an interleaved SEPIC converter with integrated magnetics for the offline LED lighting applications with LED current dimmable and input power factor correction. The converter is controlled with voltage mode PWM and run in discontinuous conduction mode. The inductor current follows the input voltage, therefore, the converter has high power factor, and can handle high power with reduced number of component count. This circuit has the advantages of (1) one stage of power conversion, (2) high power factor, (3) reduced size of the input filter, (4) reduced size of output filter, (5) integrated magnetic components, and reduced component count, (6) simple feedback control and no need to sense the input voltage, (7) voltage step-up and down, and (8) dimmable load current. It is particular suitable for the non-isolated offline applications, such as high brightness LED lighting applications. The critical design constraints and equations for both the power stage and control loop are highlighted and detailed. A practical evaluation board with 110 V input and 60 V 700 mA output is developed to verify the proposed design.

Determination of high-frequency circulating current is important for coupled inductor design of paralleled voltage source inverters (VSIs). A time-domain model describing the circulating current of coupled inductor within a switching period is presented in this article. Using this model, the peak or rms values of circulating current can be calculated for different pulsewidth modulation (PWM) methods. Both the conventional 180° interleaved PWM and zero-common-mode voltage PWM algorithms are studied here. Considering the saturation nature of the magnetic cores in determining the effective inductance of coupled inductors, the variable switching frequency PWM (VSFPWM) is proposed to better utilize the coupled inductor's saturation limit, which is determined by high-frequency circulating current peak value. With the proposed strategy, both switching losses and electromagnetic interference are improved with respect to the constant switching frequency PWM. Moreover, the detailed power losses analysis of paralleled VSIs has been presented and the dynamic performance of the proposed VSFPWM has been well investigated. Finally, the proposed method has been extended to the system with 2N paralleled inverters. Detailed simulation and experimental results are provided to validate the proposed method.

The existence of Pulse Width Modulation (PWM) switching period of a brushless dc motor (BLDCM) drive may cause commutation delay problem, especially when there are few switching periods (Tu) within one step. In this paper, this commutation delay problem was analyzed and calculated, the relationship between the number of Tu in one step and the instantaneous fluctuation magnitude of stator current was deduced. The simulation and experiment results verified the accuracy of the analysis. The results in this paper are useful for further understanding of BLDCM operating process and quantitatively choosing the optimal switching period of some BLDCM drive.