Deep‐Submicrometer Complementary Metal‐Oxide‐Semiconductor Transistors Based on Carbon Nanotube Films

Low-dimensional semiconductor-based field-effect transistor (FET) biosensors are promising for label-free detection of biotargets while facing challenges in mass fabrication of devices and reliable reading of small signals. Here, we construct a reliable technology for mass production of semiconducting carbon nanotube (CNT) film and FET biosensors. High-uniformity randomly oriented CNT films were prepared through an improved immersion coating technique, and then, CNT FETs were fabricated with coefficient of performance variations within 6% on 4-in. wafers (within 9% interwafer) based on an industrial standard-level process. The CNT FET-based ion sensors demonstrated threshold voltage standard deviations within 5.1 mV at each ion concentration, enabling direct reading of the concentration information based on the drain current. By integrating bioprobes, we achieved detection of biosignals as low as 100 aM through a plug-and-play portable detection system. The reliable technology will contribute to commercial applications of CNT FET biosensors, especially in point-of-care tests.

The excellent performance and radiation-hardness potential of carbon nanotube (CNT) field effect transistors (CNTFETs) have attracted wide attention. However, top-gate structure CNTFETs, which are often used to make high-performance devices, have not been studied enough. In this paper, the total ionizing dose (TID) effect of the top-gate structure CNTFETs and the influence of the substrate on top-gate during irradiation are studied. The parameter degradation caused by the irradiation- and radiation-damage mechanisms of the top-gate P-type CNTFET were obtained by performing a Co-60 γ-ray irradiation test. The results indicate that the transfer curves of the top-gate P-type CNTFETs shift negatively, the threshold voltage and the transconductance decrease when TID increases, and the subthreshold swing decreases first and then increases with the increase in TID. The back-gate transistor is constructed by using the substrate as a back-gate, and the influence of back-gate bias on the characteristics of the top-gate transistor is tested. We also test the influence of TID irradiation on the characteristics of back-gate transistors, and reveal the effect of trapped charge introduced by radiation on the characteristics of top-gate transistors. In addition, the CNTFETs that we used have obvious hysteresis characteristics. After irradiation, the radiation-induced trapped charges generated in oxide and the OH groups generated by ionization of the CNT adsorbates aggravate the hysteresis characteristics of CNTFET, and the hysteresis window increases with the increase in TID.

Carbon nanotubes (CNT) field-effect transistor (CNTFET) could be a possible alternative to CMOS technology for future VLSI applications. In this work, a comparative study has been carried out on the effects of technology nodes and logic styles on power dissipation, delay, leakages, etc. The technology nodes that are considered here are 90 nm and 32 nm MOSFET technology, and 32 nm CNTFET technology. The logic families considered here are the conventional complementary metal-oxide-semiconductor (CMOS), complementary pass transistor logic (CPL) and transmission gate (TG). The digital circuits considered are NAND, NOR, XOR and MUX gates. HSPICE simulations have been carried out and observed that at 32 nm CNTFET technology, the least power, worst-case delay and least PDP are found as 15.5 nW, 3.11 ps and 0.048 aJ, respectively. It is witnessed that CNTFET-based logics are superior compared to other logic families at different technology nodes.

We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate full 1 Kbit 6 transistor (6T) SRAM arrays fabricated with CNFET CMOS (totalling 6,144 p-and n-type CNFETs), with all 1,024 cells functioning correctly without any per-unit customization. We demonstrate robust operation by writing and reading multiple patterns to the Kbit arrays and characterize single-cell SRAM variability (write and read margins) and repeat cycling of cells. Due to low-temperature BEOL-compatible processing, CNFET SRAM enables new opportunities for digital systems, since: (1) CNFET SRAM can be fabricated directly on top of computing logic, and (2) buried power rails (i.e., as in our demonstration where the power rails are fabricated underneath the FET) can potentially enable smaller-area SRAM layouts.

Traditional silicon complementary metal-oxide semiconductor (CMOS) field-effect transistor (FET) technology has been pushed to 14 nm node and was predicted to arrive at its absolute performance limit in the near future. Therefore, a new transistor technology is urgently needed to replace or supplement Si CMOS and to extend Moore’s Law. Owing to its ultra-thin body and ultra-high carrier mobility, carbon nanotube (CNT) has been considered as one of the most promising channel material to replace silicon at post-Moore’s Law era. During the last 20 years, great progresses have been made on carbon nanotube field-effect transistors (CNTFETs) by researchers. In this review paper, we retrospect some key technologies of CNTFET, including carbon nanotube N-type ohmic contact ballistic transistors, doping-free complementary metal-oxide semiconductor (CMOS) technology, self-aligned high κ dielectric top gate geometry and length scaling of CNTFETs, etc. Besides, some challenges on the further development of CNTFETs, such as the preparation of high density and pure semiconducting CNT channel material at large scale and the contact performance during contact length scaling down, are discussed and the possible corresponding solutions are put forward. Based on the results of analysis and simulations, we make projections for the development of CNTFETs, which demonstrate great potential in the future. By effectively optimizing the CNT material quality and the device structure, CNTFETs may strikingly outperform the silicon counterparts at corresponding technology node and become competitive information processing devices at post-Moore’s Law era.

Three different carbon nanotube (CN) field-effect transistor (CNFET) designs are compared by simulation and experiment. While a C-CNFET with a doping profile similar to a "conventional" (referred to as C-CNFET in the following) p-or n-MOSFET in principle exhibits superior device characteristics when compared with a Schottky barrier CNFET, we find that aggressively scaled C-CNFET devices suffer from "charge pile-up" in the channel. This effect which is also known to occur in floating body silicon transistors deteriorates the C-CNFET off-state substantially and ultimately limits the achievable on/off-current ratio. In order to overcome this obstacle we explore the possibility of using CNs as gate-controlled tunneling devices (T-CNFETs). The T-CNFET benefits from a steep inverse subthreshold slope and a well controlled off-state while at the same time delivering high performance on-state characteristics. According to our simulation, the T-CNFET is the ideal transistor design for an ultrathin body three-terminal device like the CNFET.

The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects necessary for today's grail in CNFET technology, achieving functional immunity to Carbon Nanotube (CNT) manufacturing issues (such as mispositioned CNTs and metallic CNTs) is of paramount importance. In this work we present a new design technique to build compact layouts while ensuring 100% functional immunity to mispositioned CNTs. Then, as second contribution of this work, we have developed a CNFET Design Kit (DK) to realize a complete design flow from logic-to-GDSII traversing the conventional CMOS design flow. This flow enables a framework that allows accurate comparison between CMOS and CNFET-based circuits. This paper also presents simulation results to illustrate such analysis, namely, a CNFET-based inverter can achieve gains, with respect to the Energy-Delay Product (EDP) metric, of more than 4× in delay, 2× in energy/cycle and significant area savings (more than 30%) when compared to a corresponding CMOS inverter benchmarked with an industrial 65nm technology.

In recent years, carbon nanotube (CNT) emerged as one of the promising materials that shows various advantages over silicon material (e.g., aggressive channel length scaling due to absence of mobility degradation, variable bandgap with single material, ultra-thin body device that is possible due to smaller diameter [1-3nm], and compatibility of CNT with high-k materials resulting in high ION). Moreover, CNTs show both metallic and semiconducting properties; hence, by using metallic CNTs, interconnects can be realized to fabricate a circuit purely consisting of CNTs. This chapter will provide introduction to carbon nanotubes field effect transistor (CNTFETs) starting from material properties of carbon nanotubes and followed by how it can be used as semiconductor channel in field effect transistor (MOSFET) to form CNTFET. The different types of CNTFETs will be discussed based on the type of CNT used along with their advantages and disadvantages.

Carbon Nanotube Field Effect Transistors (CNFETs), consisting of semiconducting single-walled Carbon Nanotubes (CNTs), show great promise as extensions to silicon CMOS and in large-area electronics. While there has been significant progress at a single-device level, a major gap exists between such results and their transformation into VLSI CNFET technologies. Major CNFET technology challenges include mis-positioned CNTs, metallic CNTs, and wafer-scale processing. We present design and processing techniques to overcome these challenges. Experimental results demonstrate the effectiveness of the presented techniques. Mis-positioned CNTs can result in incorrect logic functionality of CNFET circuits. A new layout design technique produces CNFET circuits for arbitrary logic functions that are immune to a large number of mis-positioned CNTs. This technique is significantly more efficient compared to traditional defect- and fault-tolerance. Furthermore, it is VLSI-compatible and does not require changes to existing VLSI design and manufacturing flows. A CNT can be semiconducting or metallic depending upon the arrangement of carbon atoms. Typical CNT synthesis techniques yield ~33% metallic CNTs. Metallic CNTs create source-drain shorts in CNFETs resulting in excessive leakage (I on /I off on /I off in the range of 103−105, and overcome the limitations of existing metallic-CNT removal techniques. The above techniques are demonstrated for complex logic structures using wafer-scale growth of (99.5%) aligned CNTs on single-crystal quartz and wafer-scale CNT transfer from quartz to silicon. Such an integrated approach enables experimental demonstration of cascaded CNFET logic circuits.

Progress in the controlled synthesis and post-growth treatment of carbon nanotubes has led to the fabrication of nanotube-based field-effect transistors with intrinsic performance close to the ballistic limits. However, nanotube-based integrated circuits (ICs) developed to date typically have a working frequency of less than 1 MHz, which is well below the working frequency of silicon ICs. Here we show that the speed of carbon nanotube ICs can be significantly improved by optimizing device structure and fabrication processes, yielding ICs that work in the gigahertz regime. Based on high-performance nanotube film field-effect transistors, five-stage ring oscillators were batch fabricated and shown to exhibit an oscillation frequency of up to 5.54 GHz. This is twenty times higher than that of the leading nanotube IC (a five-stage ring oscillator with an oscillation frequency of 282 MHz). Using field-effect transistors made from carbon nanotube films, five-stage ring oscillators can be fabricated that exhibit an oscillation frequency of up to 5.54 GHz.

Carbon nanotubes (CNTs) and carbon nanotube field effect transistors (CNFETs) have demonstrated extraordinary properties and are widely accepted as the building blocks of next generation VLSI circuits. However, no nanoelectronic architecture has been proposed which is solely based on carbon nanotubes and carbon nanotube field effect transistors. The reasons include lack of a self-assembly technology which could form complex carbon nanotube structures, or, absence of a reconfigurable carbon nanotube device which could provide functionality, reliability, and performance via reconfigurability. In this paper, I propose a novel double gate carbon nanotube field effect transistor (RDG-CNFET), which is reconfigurable to be open, short, FET, or via. Layers of orthogonal carbon nanotubes with electrically bistable molecules sandwiched at each crossing form a dense array of RDG-CNFETs and programmable interconnects, and constitute a nanoelectronic architecture of manufacturability (via regularity), reliability (via reconfigurability), and performance (via device density). Simulation based on CNFET and molecular device compact models demonstrates superior logic density, reliability, performance and power consumption of the proposed RDGCNFET based nanoelectronic circuits compared with the existing, e.g., molecular diode/MOSFET based nanoelectronic circuits.

Variability and reliability analysis of CNFET technology: Impact of manufacturing imperfections

Due to extraordinary physical and electrical properties, carbon nanotubes have become one of the most promising technologies that might someday pick up where conventional CMOS devices leave off. This paper details analysis of power and delay performance of carbon nanotube field effect transistor- based universal logic gates (NAND and NOR gates). Though electrolyte-gated carbon nanotube field effect transistor have exhibited the highest performance than top-gated and back-gated carbon nanotube field effect transistor, the work demonstrates that energy delay product and switching time performance of 30nm channel length top-gated carbon nanotube field effect transistor - based NAND gate is much better than 20nm channel length electrolyte-gated carbon nanotube field effect transistor technology. As the performance of p type carbon nanotube field effect transistor is better than n type carbon nanotube field effect transistor, 30nm channel length top-gated carbon nanotube field effect transistor-based NOR gate is 4% faster than corresponding NAND gate and its energy delay product is 46% lesser than that of NAND gate.

Monte Carlo study of coaxially gated CNTFETs: capacitive effects and dynamic performance

Successful integration of carbon nanotubes (CNTs) in electronic devices and sensors requires controlled deposition at well defined locations and appropriate electrical contacts to metal electrodes/leads. Controlled self-assembly of CNTs can be achieved by interfacing them with biological molecule like DNA using its self-recognition property. However, these biointerfaces can produce undesirable changes in their device characteristics. Herein, we report an extensive study of effect of DNA interfacing on device characteristics of carbon nanotube field effect transistors and explored its synergistic effects as self-assembling element in future nanodevices. Single walled carbon nanotubes (SWNTs) are interfaced with DNA (via both covalent and non-covalent methodology) and electronic transport properties of corresponding field effect transistor devices have been studied in order to have an insight into changes in the electrical properties of SWNTs after interfacing. It was concluded that covalently linked DNA is not appropriate for self-assembly of carbon nanotubes in future nanodevices as it ruins its electrical characteristics.