Design and analysis of parity-check-code-based optical recording systems

Low-density Parity check codes (LDPC) are gaining interest for high data rate application in both terrestrial and spatial communications which requires low bit error rate. This paper proposes an algorithm through which the best parity check matrix is obtained for irregular low density parity check codes, which reduces the Bit Error Rate ,Frame Error Rate and computational complexity. Tanner graph also called a bipartite graph format in an Low Density Parity Check (LDPC) code design contains many short cycles; it will produce a computational complexity in a code design process and it degrades the code performance. To overcome this effect, we proposed an new algorithm which obtains a best final parity check matrix. Throughout the paper we will give the detailed description of an efficient algorithm proposed. The complexity is studied graphically and analytically. Using proposed algorithm, cycles of length four observed in corresponding matrix are removed. Each matrix is evaluated over a noisy Additive White Gaussian Noise (AWGN) channel. Bit Error rate and Frame error rate is calculated. The results are compared with randomly generated best parity check matrix. Simulation results shows that proposed method successfully overcomes the computational complexity and meets the near Shannon limit.

This paper proposes a general and systematic way to efficiently combine constrained codes with parity-check (PC) codes for optical recording. The proposed constrained PC code includes two component codes: the normal constrained (NC) code and the parity-related constrained (PRC) code. They are designed based on the same finite state machine (FSM). The code rates are only a few tenths below the theoretical maximum. The parity-check constraint is defined by the generator matrix (or generator polynomial) of a linear binary PC code, which can detect any type of dominant error events as well as error event combinations of the system. Two approaches are proposed to design the code in the non-return-to-zero-inverse (NRZI) format and the non-return-to-zero (NRZ) format, respectively. Designing the codes in NRZ format may reduce the number of parity bits required for error detection and simplify post-processing for error correction. Finally, examples of several newly designed codes and their performances are illustrated

This letter gives a random construction for Low Density Parity Check (LDPC) codes, which uses an iterative algorithm to avoid short cycles in the Tanner graph. The construction method has great flexible choice in LDPC code’s parameters including codelength, code rate, the least girth of the graph, the weight of column and row in the parity check matrix. The method can be applied to the irregular LDPC codes and strict regular LDPC codes. Systemic codes have many applications in digital communication, so this letter proposes a construction of the generator matrix of systemic LDPC codes from the parity check matrix. Simulations show that the method performs well with iterative decoding.

This dissertation presents a systematic exposition on finite-block-length coding theory and practice. We begin with the task of identifying the maximum achievable rates over noisy, finite-block-length constrained channels, referred to as (e, n)-capacity Cen, with e denoting target block-error probability and n the block length. We characterize how the optimum codes look like over finite-block-length constrained channels. Constructing good, short-block-length error-correcting codes defined on sparse graphs is the focus of the thesis. We propose a new, general method for constructing Tanner graphs having a large girth by progressively establishing edges or connections between symbol and check nodes in an edge-by-edge manner, called progressive edge-growth (PEG) construction. Lower bounds on the girth of PEG Tanner graphs and on the minimum distance of the resulting low-density parity-check (LDPC) codes are derived in terms of parameters of the graphs. The PEG construction attains essentially the same girth as Gallager's explicit construction for regular graphs, both of which meet or exceed an extension of the Erdos-Sachs bound. The PEG construction proves to be powerful for generating good, short-block-length binary LDPC codes. Furthermore, we show that the binary interpretation of GF(2b) codes on the cycle Tanner graph TG(2, dc), if b grows sufficiently large, can be used over the binary-input additive white Gaussian noise (AWGN) channel as good code for optimum and good code for iterative decoding. Codes on sparse graphs are often decoded iteratively by a sum-product algorithm (SPA) with low complexity. We investigate efficient digital implementations of the SPA for decoding binary LDPC codes from both the architectural and algorithmic point of view, and describe new reduced-complexity derivatives thereof. The unified treatment of decoding techniques for LDPC codes provides flexibility in selecting the appropriate design point in high-speed applications from a performance, latency, and computational complexity perspective.

Harvesting energy from radio frequency signals along with transmitting data through them is appealing for different wireless communication scenarios, such as radio frequency identification (RFID) systems and implantable devices. In this paper, we propose a technique to design nonlinear codes for the use in such systems taking into account both energy transmission and error rate requirements. In particular, we propose using concatenation of a nonlinear trellis code (NLTC) with an outer low-density parity-check (LDPC) code. We design the NLTC based on maximization of its free distance. We give necessary and sufficient conditions for its catastrophicity; in order to avoid catastrophic codes, we connect each designed NLTC to a corresponding linear convolutional code allowing for the use of simpler conditions for verification. Furthermore, we use EXIT charts to design the outer LDPC code while fixing the inner NLTC. Via examples, we demonstrate that our designed codes operate at ∼ 0.8 dB away from the information theoretic limits, and they outperform both regular LDPC codes and optimized irregular LDPC codes for additive white Gaussian noise (AWGN) channels. In addition, we show that the proposed scheme outperforms the reference schemes of concatenating LDPC codes with nonlinear memoryless mappers and using classical linear block codes in a time switching mode. © 2016 IEEE.

In Japan, the next generation of Integrated Services Digital Broadcasting — Terrestrial (ISDB-T) system is being developed for transmission of large-volume content services such as ultra high definition television (UHDTV). The system uses low density parity check (LDPC) code as the forward error correction (FEC) to improve its robustness. In particular, the performance of the system's FEC should be evaluated not only in additive white Gaussian noise (AWGN) environments, but also in multipath environments. Moreover, it would be desirable for the new FEC to have better performance than the previous one even in multipath environments. Previous research evaluated the transmission performance of LDPC code by using computer simulations of the propagation model. The actual propagation characteristics were not evaluated. In this paper, we describe the transmission performance of convolutional coded orthogonal frequency division multiplexing (CC-OFDM) and LDPC coded OFDM (LDPC-OFDM) in computer simulations using the same OFDM frame structure and propagation channels as measured in an outdoor experiment conducted in an urban area. We show that LDPC code outperforms CC in multipath environments and how the transmission performance depends on the code rate. In addition, we analyze the correlation between transmission performance and propagation channels.

Cooperative communication is a well known technique to yield transmit diversity in the case of fading channels and to increase the spectral efficiency in the case of Gaussian channels. Error-correcting codes have to be carefully designed to achieve the promised gains. Good LDPC codes are known for fading channels and for Gaussian channels, but an LDPC code ensemble that performs well on both channels has not yet been presented in the literature. This paper merges two families of LDPC codes into a universal LDPC code ensemble for both fading channels and Gaussian channels. Furthermore, the new universal LDPC code ensemble outperforms previously proposed codes on the block fading channel, which is explained through a fading space analysis. Simulation of the word error rate performance of the new proposed family of LDPC codes shows that it performs well on both fading channels and Gaussian channels.

This paper presents a technique to obtain an expurgated union bound on the frame error rate (FER) of space-time trellis codes (STTCs) on quasi-static Rician fading channels. We first present an algorithm to compute the distance spectrum of STTCs. The proposed algorithm iteratively manipulates the entries of the transition matrix of the product state transition diagram, which is convenient for symbolic computation. Then, a new method to identify the dominant quasi-static fading error events is proposed. Comparisons with simulated results reveal that the expurgated union bound on the FER (obtained using the limiting-before-average technique) using these dominant error events is tight.

New multivariate noise model and data detection using the expectation maximization algorithm

CP-EBPSK with random-polar is a class of highly efficient modulation technology, where the phase changing during modulation interval is controlled by a random sequence. The performance of the coded CP-EBPSK modem with random-polar has not been revealed yet. In this paper, the error-correcting codes, including RS code, convolutional code and LDPC code, are introduced to this system for the first time, and the performance of the coded CP-EBPSK modulation with random-polar in AWGN channel is also simulated. Simulation results show that: 1) the coded system can improve the transmission performance largely, 2) among these three error-correcting codes, the LDPC code can derive the best coding gain.

We consider the challenges of finding good puncturing patterns for rate-compatible low-density parity-check code (LDPC) codes over additive white Gaussian noise (AWGN) channels. Puncturing is a scheme to obtain a series of higher rate codes from a lower rate mother code. It is widely used in channel coding but it causes performance is lost compared to non-punctured LDPC codes at the same rate. Previous work, considered the role of survived check nodes in puncturing patterns. Limitations, such as single survived check node assumption and simulation-based verification, were examined. This paper analyzes the performance according to the role of multiple survived check nodes and multiple dead check nodes. Based on these analyses, we propose new algorithm to find a good puncturing pattern for LDPC codes over AWGN channels.

This chapter discusses fundamentals of information theory and channel coding (error correction coding ECC, Forward error correction FEC). First, key results of Shannon, including channel capacity and the relationship between transmit power and bandwidth, are discussed. Block codes multiply a block of data with an encoding matrix. For systematic codes, the resulting codeword consists of systematic bits and parity check bits. Decoding is achieved by multiplication with a parity check matrix and determination of the syndrome vector. Correction of errors within the correction sphere can be done, e.g., through lookup tables. Convolutional codes send the source data stream through shift registers and adders, a process described by a trellis diagram. Maximum-likelihood sequence estimation (Viterbi algorithm) determines the (transmit) bit sequence with best distance metric (Hamming or Euclidean) from the received signal. Methods for combining coding and higher-order modulation include trellis coded modulation (using set partitioning for code design) and bit-interleaved coded modulation (BICM). Turbo codes are close to capacity-achieving. They are based on transmitting differently interleaved convolutional codes; receivers use soft decoding of the constituent codes and iterative exchange of soft information (log-likelihood ratios). Low-density parity check codes (LDPCC) are decoded by belief propagation (message passing), where variable nodes and constraint nodes exchange beliefs about the codeword. In fading channels, (block or convolutional) interleaving is essential to provide diversity. From an information-theoretic point of view, in fading channels we can distinguish between the ergodic capacity and the outage capacity. If the channel state information is known at the transmitter, waterfilling is the optimum power allocation strategy. Automatic Repeat Request ARQ) and Hybrid ARQ (including chase combining or incremental redundancy) are described in the appendix.

In order to solve high encoding complexities of irregular low-density parity-check (LDPC) codes, a deterministic construction of irregular LDPC codes with low encoding complexities was proposed. And the encoding algorithms were designed, whose complexities are linear equations of code length. The construction and encoding algorithms were derived from the effectively encoding characteristics of repeat-accumulate (RA) codes and masking technique. Firstly, the new construction modified parity-check matrices of RA codes to eliminate error floors of RA codes. Secondly, the new constructed parity-check matrices were based on Vandermonde matrices, this deterministic algebraic structure was easy for hardware implementation. Theoretic analysis and experimental results show that, at a bit-error rate of 10×10−4, the new codes with lower encoding complexities outperform Mackay’s random LDPC codes by 0.4–0.6 dB over an additive white Gauss noise (AWGN) channel.

The multiple description coding framework is well-suited for the transmission of images in the presence of transmission errors. However, it has been mainly explored for idealized channels, where packets are either received correctly or not at all. In more realistic scenarios, bitstreams are affected by bit-level noise and error correcting codes must be employed. In the proposed scheme, the input image is decomposed into wavelet coefficients that are encoded using lattice vector quantization for the generation of multiple descriptions. Low-density parity-check (LDPC) codes are used for the protection of each stream, while joint decoding exploits the correlation between the multiple descriptions. The proposed joint source-channel decoding scheme can provide robust transmission of images by introducing a controlled amount of redundancy that can be used for error recovery. Results are presented for image transmission over binary symmetric and Gaussian channels.

Low Density Parity Check (LDPC) are the linear error correction codes for amendment of mistakes, a technique of transmitting the messages over the noisy channel. With lieu- Shannon’s controlled implementation and typically parallel execution of plan, low-density parity check codes are mainly executed at enquire and well-designed area of applications. Bipartite graph is used for development of LDPC codes. LDPC being limit stirring in the direction of codes which means its actual building exists that enables outer edge to be closely intended for symmetry of a channel with no memory. FPGA or Field Programmable Gate Array is based on configurable logic block (CLB) and is a semiconductor gadget that is associated by virtue of programmable interconnects. FPGAs are highly robust and can be created or designed as per the application or usefulness prerequisite of application. This research paper presents adaptable and more compatible LDPC decoder in change for other general LDPC decoder. This decoder has a completely adaptable LDPC plan in FPGA, which supports distinct codes and rate of information. The design is implemented in Xilinx ISE 14.2 software using VHDL programming and synthesized on SPARTAN 3E FPGA. Keywords: Sparse bipartite graph, threshold, Shannon limit, Very High Speed Integrated Circuit Hardware Description Language (VHDL) Cite this Article Sachit Gupta, Richa, Adesh Kumar. FPGA Implementation of LDPC Codes. Journal of Telecommunication, Switching Systems and Networks . 2018; 5(1): 21–28p.