Design and Analysis of Single Precision Floating Point Multiplication with Vedic Mathematics Using Different Techniques

Reversible logic preserves information and provides low power computing. Floating point multiplier is an important part of arithmetic in DSP applications. IEEE754 provide two basic and widely used formats for representing floating point numbers namely Single Precision Floating point (SPFP) and Double Precision Floating Point (DPFP). In this paper, we have proposed designs for Reversible SPFP and DPFP point multiplier which requires optimum design of 24X24 and 53X53 multiplying circuitry with reversible gates respectively. Also we presented sign bit calculation and exponent bit calculation circuits by reversible logic. Reversible Mantissa bits calculation circuitry requires consumes more area as it has large value of quantum cost and garbage outputs as compare to reversible sign bit and exponent bits calculation circuitry. So, we mainly focused our work on to minimize the area consumed by the reversible mantissa bits calculation circuit by minimizing the value of quantum cost and garbage outputs of it. In this paper, we presented two ways for partial products generation with reversible gates. We propose a new design of reversible 12X12 reversible Wallace tree multiplier for single precision and double precision mantissa multiplier circuit. Also 5X5 and 5X12 reversible Wallace tree multiplier for double precision multiplier. Here we use the optimized designs of reversible half adder, Full adder and 4:2 compressors. In the final summation stage, we carefully shifted the product terms and add them. For this stage we have carefully chosen the adders and compressor in such way to get the optimized results in terms of quantum cost and Garbage output. We have also shown the improvement in single precision floating point multiplier in terms of Quantum cost and Garbage output.

This paper describes a single precision floating point division based on Newton-Raphson computational division algorithm. The Newton-Raphson computational algorithm is implemented using 32-bit floating point multi-plier and subtractor. The salient feature of this proposed design is that the module for computing mantissa in 32-floating point multiplier is designed using a 24-bit Vedic multiplication (Urdhva-triyakbhyam-sutra) technique. 32-bit floating point multiplier, designed using Vedic multiplication technique, yields a higher computational speed, hence, is efficiently used in floating point divider. Another important feature is the efficient use of device utilization parame-ters and reduced power consumption. An advantage of the Newton-Raphson algorithm is the higher versatility and precision. For representing 32-bit floating point numbers, IEEE 754 standard format is used. ISim simulator is used for simulation. The proposed floating point divider is designed using Verilog Hardware Description Language (HDL) and is verified on Xilinx Spartan 6 SP605 Evaluation Platform FPGA.

A design and implementation of a 32 bit fast floating point multiplier with the single precision IEEE 754-2008 standard target for Xilinx virtex-5 FPGA. The proposed design and timing information of the multiplier sub-module has been calculated and the proposed design intends to increase the speed on the multiplier by reducing delay at every stage using optimal adder design. The proposed multiplier is made to multiply two floating point numbers and generate the output to make minimum time delay. The modules have been written in verilog HDL and it is simulated using the Xilinx ISE12.1 targeted on the FPGA.

The design of low power multipliers is the basic necessity for the design and the implementation of efficient power aware devices. Multipliers play a major role in digital signal processing applications. In multiplication, reliability is strongly affected by power consumption. Here Vedic multiplier is designed by the principles of Vedic mathematics which is the ancient Indian system of mathematics. In this paper four 4*4 Vedic multipliers are designed based on four different logic full adders such as 28T, TGFA, 14T and 16T. These multipliers and full adders were designed and simulated using microwind 2 electronic design automation tool with 0.12μm technology. Finally a comparison is made on the performance of full adders and Vedic multipliers based on power consumption and transistor count.

This paper illustrates the implementation of Multiply-Accumulate unit (MAC) to improve performance using the Ancient Indian Vedic Mathematics. Real-time signal processing needs high speed and high yield Multiplier-Accumulator (MAC) unit that consumes less power, which is always a key to achieve a high performance digital signal processing system. Speed of the multiplier is essential to MAC unit. Vedic Mathematics is the ancient mathematics. There are sixteenth unique sutras in the Vedic mathematics. The Sutras saves effort and time required in solving the problems as compared to the formal methods. The Sutra “Urdhav Triyagbhyam” (Vertical and Crosswise) is used inside the MAC unit as a multiplier. The coding is done in VHDL, synthesis is done in Xilinx ISE series and the FPGA synthesis is done using Xilinx Spartan library. The results show that design of MAC unit using Vedic multiplication is much more efficient in terms of delay and speed compared to conventional multiplication.

The Vedic multiplier is derived from the ancient mathematics called Vedic mathematics .The ancient mathematics has different sutras in that we use Urdhva Tiryagbhyam sutra which means clock wise and vertically . As we know that binary multiplication is not possible so that instead we use binary addition or subtraction instead of it. The key process for the multiplication is the speed of the processor. The fastest mode of multiplication is the Vedic multiplier. In this paper we want to show the delay and utilization of components available for the multiplier by executing the code. The comparison of delay from some papers was also proposed in this paper. The research is going on the Vedic mathematics to overcome the problems on the conventional mathematics. In future Vedic multiplier plays an important role in the DSP (Digital Signal Processing).As it is the fastest and efficient mode of operation. In this paper I am calculating the bit wise delay up to 32-bit. The whole analysis was done in Xilinx. The ISM wave forms for every bit up to 32-bit was to be obtained. The utilization, used, available, utilized analysis was also taken. The whole process was done in XILINX software.

Matrix multiplication is a common technique for increasing the computational speed of scientific and engineering tasks. The matrix multiplier is designed in this paper utilizing an optimized Vedic multiplier. Vedic mathematics, which is a collection of sutras for doing mathematical arithmetic simply and more speedily, is utilized to speed up multiplication. These sutras aid in the reduction of several processors performance metrics, such as power and delay. As a result, the current multiplier approaches are replaced with Urdhva Tiriyagbhyam, a Vedic Math multiplication methodology. We used 1:8 demultiplexer-based Full Adders (DFAs) to create the Vedic Multiplier to circumvent the power constraint. As a result, the overall power of matrix multiplication was improved across various bits. The Optimized Matrix multiplier is designed in Verilog HDL, and the Nexys DDR4 of the Artix-7 series is utilized as the target device for synthesis.

In this paper, the design of Multilevel 2d-DWT with novel Vedic multiplier is presented. In 2d-DWT structure, Digital FIR filter is used to increase the image resolution and eliminate the unwanted noise present in the image. Conventional three level 2d-DWT is designed using regular Vedic multiplier. But it consumes more area and power. And also less image resolution. So MAC unit in the FIR filter is changed to design the efficient FIR filter. Some inputs do not produce the required outputs in conventional MAC units using regular Vedic multiplier. A novel Vedic multiplier with less number of half adders and Full Adders is proposed in order to overcome such an error. Simulation is done in Matlab2008a and Modelsim6.3c. Synthesis and Implementation is performed by Xilinx and FPGA Spartan3.

Floating point numbers are used in computations in the field of signal processing and multimedia. The multiplication process requires more hardware resources and processing time when compared with addition and subtraction. The Processing speed of the multipliers decides the execution time of the system as it consumes most of the time. In this paper, Complex floating point multiplication using Vedic multiplier, array multiplier and CIFM multiplier is implemented using Verilog on VIVADO DESIGN SUITE 2018.3 and their performance is compared.

Diffraction calculations in few-bit formats, such as single-precision floating-point and fixed-point numbers, are important because they yield faster calculations and lower memory usage. However, these methods suffer from low accuracy owing to the loss of trailing digits. Fresnel diffraction is widely known to prevent the loss of trailing digits. However, it can only be used when the paraxial approximation is valid. In this study, a few-bit diffraction calculation method that achieves high accuracy without using any approximation is proposed. The proposed method is derived only by rationalizing the numerator of conventional formulas. Even for scenarios requiring double-precision floating-point numbers using conventional methods, the proposed method exhibits higher accuracy and faster computation time using single-precision floating-point numbers.

The hardware realization of fast fourier transform (FFT) consists of complex arithmetic operations such as multiply and accumulate. The key idea of this paper is to implement the 8-point Radix-2 DIT (Decimation In Time) FFT. In the FFT algroithm the twiddle factor generation by traditional method of generating sine and cos is replaced by the CORDIC algorithm for trigonometric functions. For the multiply and accumulate unit, different multipliers were used namely CORDIC multiplier, Single precision floating point multiplier. The adder blocks used in the implementation are linear adders such as Ripple Carry Adder (RCA) and parallel prefix adders such as Kogge-Stone Adder (KSA). Different combinations of multipliers and adders are used in the implementation of FFT, using VHDL in VIVADO 2016.2 version and programmed it in Xilinx ZYNQ FPGA board. The FFT implementation using single precision floating point multiplier incorporated with CORDIC multiplier and koggestone adder gives better delay performance compared to other combinations. In terms of area the combination of CORDIC multiplier with Ripple carry adder performs best.

Power dissipation problem is one of the most challenging problems in designing conventional electronic circuits. One of the best approaches to overcome this problem is to design reversible circuits. Nowadays, reversible logic is considered as a new field of study that has various applications such as optical information processing, design of low power CMOS circuits, quantum computing, DNA computations, bioinformatics and nanotechnology. Due to the vulnerability of the digital circuits to different environmental factors, the design of circuits with error-detection capability is considered a necessity. Parity preserving technique is known as one of the most famous methods for providing error-detection ability. Multiplication operation is considered as one of the most important operations in computing systems, which can play a significant role in increasing the efficiency of such systems. In this paper, two efficient 4-bit reversible multipliers are proposed using the Vedic technique. The Vedic technique is able to increase the speed of multiplication operation by producing partial products and their sums simultaneously in a parallel manner. The first architecture lacks the parity preserving potential, while the second architecture has the ability parity preserving. Since a 4-bit Vedic multiplier includes 2-bit Vedic multipliers and 4-bit ripple carry adders (RCA), so in the first design, TG, PG and FG gates have been used to design an efficient 2-bit reversible Vedic multiplier, as well as PG gate and HNG block have been applied as a half-adder (HA) and full-adder (FA) in the 4-bit RCAs. Also, in the second design, 2-bit parity preserving reversible Vedic multiplier has been designed using FRG, DFG, ZCG and PPTG gates as well as ZCG and ZPLG blocks have been utilized as HA and FA in the 4-bit RCAs. Proposed designs are compared in terms of evaluation criteria of circuits such as gate count (GC), number of constant inputs (CI), number of garbage outputs (GO), quantum cost (QC), and hardware complexity. The results of the comparisons indicate that the proposed designs are more efficient compared to available counterparts.

Multipliers act as processors and take on the notable work of many computing frameworks. The speed of the processor is profoundly affected by the speed of their multipliers. In order to improve the system speed, faster and more efficient multipliers should be used. A Vedic multiplier is one of the best solution that can be used to perform multiplications at a faster rate by eliminating the steps that are not needed in usual multiplication process. Power consumption is another critical issue in embedded systems that cannot be ignored. Reversible logic has become notable in the recent years because of its potential to reduce power utilization, which is a major concern in digital design. In this work, a high-speed 16 × 16 Vedic multiplier was designed using Urdhva Tiryagbhyam (UT) sutra, which is derived from Vedic mathematics. This is a simple structure as well as an unbeatable combination for creating any complex multiplication operations for services where speed is of prime importance. This work also proposes a new method based on Elliptic Curve Cryptography (ECC) system for encryption and decryption using Vedic multiplication. By using Vedic Multiplication in ECC the processing time is perfectly reduced. The proposed Elliptic curve cryptography method is much faster than other elliptic curve cryptographic algorithms. Compared to other cryptographic techniques, the key size required to provide equivalent security is small in ECC.

Modular arithmetic computations are used widely in various data security and reliability techniques. Information security systems certainly benefit from the design of energy-efficient modular exponentiation architectures. The use of low-power logic adders to realize modular exponentiation operations is very essential in prospective cryptography contexts. In this paper, various full adder circuit designs are presented which are used in developing an energy efficient modular exponentiation architecture. Here, the full adder is designed using Register Transfer Level (RTL), Standard Logic Cell (SLC), Reversible Logic Gate (RLG), and Artificial Neural Network (ANN) logic methods. All full adder designs are imposed on modular exponentiation circuit to analyze performance metrics in terms of dynamic power dissipation, Figure of Merit, and Energy Delay Product. The Modular Exponentiation architecture is designed based on the above full adders and is simulated and synthesized using Xilinx Vivado Zynq-7000 family configurable device. From the synthesis results, the dynamic power dissipation, Figure of Merit (FOM), and Energy Delay Product (EDP) of the ANN Modular Exponentiation circuit shows an improvement compared to other designs. The total power consumption, dynamic power dissipation, FOM, and EDP of ANN Full Adder and Modular Exponentiation circuit can achieve (8%, 16%), (23.5%, 20.7%), (14.7%, 14%), and (28.5%, 16%) compared to RLG Full adder and Modular Exponentiation circuit.KeywordsFeynman gateMLPerceptronSwitching activityPDPModular multiplierToffoli gate

This paper presents a high-speed Vedic multiplier based on the Urdhva Tiryagbhyam sutra of Vedic mathematics that incorporates a novel adder based on Quaternary Signed digit number system. Three operations are inherent in multiplication: partial products generation, partial products reduction and addition. A fast adder architecture therefore greatly enhances the speed of the overall process. A Quaternary logic adder architecture is proposed that works on a hybrid of binary and quaternary number systems. A given binary string is first divided into quaternary digits of 2 bits each followed by parallel addition reducing the carry propagation delay. The design doesn't require a radix conversion module as the sum is directly generated in binary using the novel concept of an adjusting bit. The proposed multiplier design is compared with a Vedic multiplier based on multi voltage or multi value logic [MVL], Vedic Multiplier that incorporates a QSD adder with a conversion module for quaternary to binary conversion, Vedic multiplier that uses Carry Select Adder and a commonly used fast multiplication mechanism such as Booth multiplier. All these designs have been developed using Verilog HDL and synthesized by Synopsys Design Compiler. They have been realized using the open source NAN gate 15nm technology library. The proposal shows a maximum of 88.75% speed improvement with respect to Multi Value logic based 128x128 Vedic multiplier while the minimum is 17.47%.