DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR

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To improve the performance of the processors, the pipeline technique is used extensively to implement I.L.P (Instruction Level Parallelism). We measure the processor performance through the quantity of Instructions Level Parallelism represented through its design. We can counterstrike the parallelism with the aid of the execution of conditional branch instructions, which might additionally break the flow of the program execution. To overcome the branch problem, numerous ways have been suggested proactive to predict both the direction as well as the address of the executed instructions. In this paper, the FPGA ( Field Programmable Gate Arrays) based implementation of the 1-bit dynamic branch predictor is presented. The 1-bit dynamic branch predictor is developed especially for conditional branch instructions. The pipeline would not detach from the instruction queue when any conditional instructions occur as a 1-bit dynamic branch predictor implements it. This technique improves processor performance by implementing a deduction in the controlling hazard in the pipeline. Modelsim and Quartus tool is used for the design and implementation of the predictor.