Design and optimization of heterogeneous tree-based FPGA using 3D technology

The authors explore and design the traditional field-programmable gate array (FPGA) interconnect topologies and architectures that can play an important role in improving performance and density. The main architectures under exploration are tree-based and island-style Manhattan Mesh. Mesh-based design is the most common industrial and academic architecture. Numerous research and industrial designs have been developed to improve mesh-based FPGAs' performance, area, and power consumption. Nonetheless, when looking at performance metrics such as speed, area, and power, the gap is generally very wide for FPGAs compared to application-specific integrated circuits (ASICs). Despite their good properties, such as high logic density and area advantage, tree-based architectures have been overlooked up to now. This article addresses long wire length issues associated with tree-based programmable interconnects using 3D design and manufacturing technologies. Using their dedicated 3D design and optimization methodology, the authors show that 3D tree-based architecture is 1.5 times faster than the mesh-based counterpart.

The book focuses on the cost/area, performance and power consumption differences between Field-Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). These differences are referred to as the gap between FPGAs and ASICs and knowledge of this gap is fundamental for people who design FPGAs, who use FPGAs, or who are considering their use. This book reviews and examines the gap in two ways. The first portion of the book focuses on measurements of the silicon area, performance, and power consumption gap. This is done by comparing designs implemented on a commercial FPGA and using an ASIC methodology. Through this comparison, various trends are noted to elucidate some of the design choices that can narrow the gap. The latter half of the book focuses on the trade-offs that can be made in the creation of a FPGA to narrow the gap selectively. This is useful because silicon area, performance and power consumption are not equally important to all users of FPGAs. The book describes the approach used to investigate these trade-offs and it includes a detailed description of the transistor sizing tool developed to assist in this investigation. The scope of the trade-offs is then examined and the effect of these trade-offs on the FPGA to ASIC gap is considered. The idea of making cost and performance trade-offs has been considered in past works but this book explores the use of transistor-sizing to enable these trade-offs.

Background: In recent years, the rising demand for high-performance radar systems in aeronautics, astronautics, national defense, and civil communication has driven the widespread application of phased-array technology. The design of beam controllers, the core of phased-array systems, faces many challenges. Traditional implementation schemes are usually based on application-specific integrated circuits (ASIC) or discrete components, which have a long development cycle, poor flexibility, and limited adaptability. Field-programmable gate arrays (FPGA), with their high parallelism, reconfigurability, and powerful signal processing capabilities, offer a new way to implement phased-array control systems. But FPGA design has traditionally relied on register transfer level (RTL) description, which is inefficient and struggles to keep up with the rapid iteration of complex algorithms. With the development of high-level synthesis (HLS) technology, it has become possible to develop FPGAs using high-level languages such as C/C++. However, improving development efficiency while ensuring hardware performance remains a key issue in the design of phased-array beam controllers. Materials and Methods: This study employs an HLS - RTL co - design method to build a phased - array beam controller. This approach combines the strengths of HLS's efficient algorithm implementation and RTL's precise hardware interface control. The system architecture consists of three parts: the host - machine control layer, FPGA processing layer, and phase - control output layer. In the FPGA processing layer, the core beam - forming algorithm is implemented via HLS. Based on phased - array principles, this algorithm converts target angles to wave vectors and calculates phase - compensation values for each element in an 8×8 array. Pipelining and parallel processing techniques are used in the HLS design to optimize algorithm throughput and latency. The phase - control output layer, designed with RTL, repackages 64 calculated phase values and distributes them to 16 physical phase - shifter chips. Each phase - shifter manages four elements and receives control data through an SPI interface. Results: The proposed FPGA-based phased-array beam controller design in this paper has successfully achieved high - speed, high - precision beam control. By using the HLS - RTL co - design method, it has solved the problem of low algorithm implementation efficiency in traditional FPGA development and ensured the high performance and reliability of hardware interfaces. Experimental results indicate that the system meets or surpasses design targets on key performance indicators. Its end - to - end latency is kept within 130μs, it supports an angle update rate of over 5,000 times per second, and can satisfy the requirements for tracking highly dynamic targets in practical applications. Conclusion: The major contributions of this research are as follows: presenting an HLS - RTL co - design methodology for complex FPGA system development; designing an efficient phased - array beam - forming algorithm and its hardware implementation; and developing a flexible and scalable phased - array control system architecture that supports different array configurations. These findings are highly significant for beamforming technologies in phased - array radar and 5G communication systems, as well as for other FPGA applications requiring high - speed signal processing.

Most applications nowadays require protection of their data from tampering to ensure secure transfer of information. At the same time, they need to be secured quickly and within available resources. In this paper, efficient hardware architecture has been designed and implemented for the Advanced Encryption Standard (AES) algorithm based on the Field Programmable Gate Array (FPGA) using High Level Language (HLL). The design focused on the optimal use of available resources, thus iterative looping architecture is suggested to minimize the hardware resources utilization and power consumption. The design is synthesized and simulated using Xilinx ISE 14.7 and ModelSim software, respectively. The implementation is compared with other previous works in terms of area, and power consumption. The results show that the proposed design achieves significant decrease in area (utilize 423 slices) and power consumption (3.68 W). The throughput reaches the value of 2457 Mbit/Sec implemented on Virtex-6 xc6vlx195t-3 of Xilinx device family. This makes the proposed design suitable for applications, where resources are limited.

Industrial designers and educators who plan to design microelectronic systems (e.g. hardware accelerators, co-processors, etc.) are increasingly capturing their designs using hardware description languages such as VHDL and Verilog. The designs are then most often synthesized into programmable logic components such as field-programmable gate arrays (FPGAs) offered by Xilinx, Altera, Actel and others. This approach places the emphasis on high-level design which reduces time to market by relying on synthesis software and programmable logic to produce working prototypes rapidly. These prototypes may then be altered as requirements change or converted into high-volume mask gate arrays or other application-specific integrated circuits (ASICs) when the demand is known to be sufficient. These ASICs, however, must be designed to be testable to screen out those with manufacturing defects. Hence, scan logic must be inserted, test vectors generated and fault grading performed to ensure a high level of testability. These efforts complicate and delay the conversion of FPGA designs to ASICs but must be considered by designers of microelectronic systems. Topics covered include: design flow; system partitioning; hardware description languages (HDLs); specifying behavioral control; specifying structural components; critical paths; placement and routing; technology choices; FPGA applications; rapid prototyping; retargeting; manufacturing defects; scan chain insertion; test vector generation; fault grading, and ASIC production

Digital watermarking is an innovative technique for intellectual property protection (IPP) of Field Programmable Gate Array (FPGA) designs. However, many of these techniques usually need manually extract marks from binary bit-files by the FPGA tool or exhaustive search to find out marks in the design, which results in inefficiency of the watermark verification. This paper presents a method to fast verify the authorship through extracting the content of the watermarked lookup tables from a binary bit-file. We demonstrate the proposed method on several Xilinx Virtex-II devices, and experimental results on the watermarked designs from the IWLS 2005 benchmarks show that the verification of authorship has high efficiency.

Chapter 6 - Board-Level Design Decisions and Allocation

Hyperspectral imagery is a class of image data which is used in many scientific areas, most notably, medical imaging and remote sensing. It is characterized by a wealth of spatial and spectral information. Over the last years, many algorithms have been developed with the purpose of finding "spectral endmembers," which are assumed to be pure signatures in remotely sensed hyperspectral data sets. Such pure signatures can then be used to estimate the abundance or concentration of materials in mixed pixels, thus allowing sub-pixel analysis which is crucial in many remote sensing applications due to current sensor optics and configuration. One of the most popular endmember extraction algorithms has been the pixel purity index (PPI), available from Kodak's Research Systems ENVI software package. This algorithm is very time consuming, a fact that has generally prevented its exploitation in valid response times in a wide range of applications, including environmental monitoring, military applications or hazard and threat assessment/tracking (including wildland fire detection, oil spill mapping and chemical and biological standoff detection). Field programmable gate arrays (FPGAs) are hardware components with millions of gates. Their reprogrammability and high computational power makes them particularly attractive in remote sensing applications which require a response in near real-time. In this paper, we present an FPGA design for implementation of PPI algorithm which takes advantage of a recently developed fast PPI (FPPI) algorithm that relies on software-based optimization. The proposed FPGA design represents our first step toward the development of a new reconfigurable system for fast, onboard analysis of remotely sensed hyperspectral imagery.

As design complexity keeps increasing, the 2.5D field-programmable gate array (FPGA) with large logic capacity has become popular in modern circuit applications. A 2.5D FPGA consists of multiple dies connected through super long lines (SLLs) on an interposer. Each die contains heterogeneous logic blocks and ASIC-like clocking architectures to achieve better skew and timing. Existing works consider these problems separately and thus may lead to serious timing issues or routing failure. This article presents an analytical placement algorithm for the 2.5D FPGA to simultaneously minimize the number of inter-die SLL signals and intra-die clocking violations. Using a lifting dimension technique, we first formulate the 2.5D global placement problem as a three-dimensional continuous and differential minimization problem, where the SLL-aware block distribution is modeled by 3D Poisson’s equation and directly solved to obtain an analytical solution. Then, we further reformulate the minimization problem as a separable optimization problem with linear constraints. Based on the proximal alternating direction method of multipliers optimization method, we efficiently optimize the separable subproblems one by one in an alternating fashion. Finally, clock-aware legalization and detailed placement are applied to legalize and improve our placement results. Compared with the state-of-the-art works, experimental results show that our algorithm can resolve all clocking constraints and reduce the number of SLL crossing signals by 36.9% with similar wirelength in a comparable running time.

Chapter 5 - FPGA Device-Level Design Decisions

This thesis work presents the implementation and validation of image processing problems in hardware to estimate the performance and precision gain. It compares the implementation for the addressed problem on a Field Programmable Gate Array (FPGA) with a software implementation for a General Purpose Processor (GPP) architecture. For both solutions the implementation costs for their development is an important aspect in the validation. The analysis of the flexibility and extendability that can be achieved by a modular implementation for the FPGA design was another major aspect. This work is based upon approaches from previous work, which included the detection of Binary Large OBjects (BLOBs) in static images and continuous video streams [13, 15]. One addressed problem of this work is the tracking of the detected BLOBs in continuous image material. This has been implemented for the FPGA platform and the GPP architecture. Both approaches have been compared with respect to performance and precision. This research project is motivated by the MI6 project of the Computer Vision research group, which is located at the Bonn-Rhein-Sieg University of Applied Sciences. The intent of the MI6 project is the tracking of a user in an immersive environment. The proposed solution is to attach a light emitting device to the user for tracking the created light dots on the projection surface of the immersive environment. Having the center points of those light dots would allow the estimation of the user’s position and orientation. One major issue that makes Computer Vision problems computationally expensive is the high amount of data that has to be processed in real-time. Therefore, one major target for the implementation was to get a processing speed of more than 30 frames per second. This would allow the system to realize feedback to the user in a response time which is faster than the human visual perception. One problem that comes with the idea of using a light emitting device to represent the user, is the precision error. Dependent on the resolution of the tracked projection surface of the immersive environment, a pixel might have a size in cm2. Having a precision error of only a few pixels, might lead to an offset in the estimated user’s position of several cm. In this research work the development and validation of a detection and tracking system for BLOBs on a Cyclone II FPGA from Altera has been realized. The system supports different input devices for the image acquisition and can perform detection and tracking for five to eight BLOBs. A further extension of the design has been evaluated and is possible with some constraints. Additional modules for compressing the image data based on run-length encoding and sub-pixel precision for the computed BLOB center-points have been designed. For the comparison of the FPGA approach for BLOB tracking a similar implementation in software using a multi-threaded approach has been realized. The system can transmit the detection or tracking results on two available communication interfaces, USB and RS232. The analysis of the hardware solution showed a similar precision for the BLOB detection and tracking as the software approach. One problem is the strong increase of the allocated resources when extending the system to process more BLOBs. With one of the applied target platforms, the DE2-70 board from Altera, the BLOB detection could be extended to process up to thirty BLOBs. The implementation of the tracking approach in hardware required much more effort than the software solution. The design of high level problems in hardware for this case are more expensive than the software implementation. The search and match steps in the tracking approach could be realized more efficiently and reliably in software. The additional pre-processing modules for sub-pixel precision and run-length-encoding helped to increase the system’s performance and precision.

Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In highsample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable GateArray (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimised to the target application to minimise component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterised implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two physical limitations: (1) The massive usage of routing multiplexers causes delay and power overheads as compared to ASICs. To reduce their power consumption, FPGAs have to operate at low supply voltage but sacrifice performance because the transistors drive degrade when working voltage decreases. (2) Using volatile memory technology forces FPGAs to lose configurations when powered off and to be reconfigured at each power Resistive Random Access Memories (RRAMs) have strong potentials in overcoming the physical limitations of conventional FPGAs. First of all, RRAMs grant FPGAs non-volatility, enabling FPGAs to be Normally powered off, Instantly powered on. Second, by combining functionality of memory and pass-gate logic in one unique device, RRAMs can greatly reduce area and delay of routing elements. Third, when RRAMs are embedded into datpaths, the performance of circuits can be independent from their working voltage, beyond the limitations of CMOS circuits. However, researches and development of RRAM-based FPGAs are in their infancy. Most of area and performance predictions were achieved without solid circuit-level simulations and sophisticated Computer Aided Design (CAD) tools, causing the predicted improvements to be less convincing. In this thesis,we present high-performance and low-power RRAM-based FPGAs fromtransistorlevel circuit designs to architecture-level optimizations and CAD tools, using theoretical analysis, industrial electrical simulators and novel CAD tools. We believe that this is the first systematic study in the field, covering: From a circuit design perspective, we propose efficient RRAM-based programming circuits and routing multiplexers through both theoretical analysis and electrical simulations. The proposed 4T(ransitor)1R(RAM) programming structure demonstrates significant improvements in programming current, when compared to most popular 2T1R programming structure. 4T1R-based routingmultiplexer designs are proposed by considering various physical design parasitics, such as intrinsic capacitance of RRAMs and wells doping organization. The proposed 4T1R-based multiplexers outperformbest CMOS implementations significantly in area, delay and power at both nominal and near-Vt regime. From a CAD perspective, we develop a generic FPGA architecture exploration tool, FPGASPICE, modeling a full FPGA fabric with SPICE and Verilog netlists. FPGA-SPICE provides different levels of testbenches and techniques to split large SPICE netlists, in order to obtain better trade-off between simulation time and accuracy. FPGA-SPICE can capture area and power characteristics of SRAM-based and RRAM-based FPGAs more accurately than the currently best analyticalmodels. From an architecture perspective, we propose architecture-level optimizations for RRAMbased FPGAs and quantify their minimumrequirements for RRAM devices. Compared to the best SRAM-based FPGAs, an optimized RRAM-based FPGA architecture brings significant reduction in area, delay and power respectively. In particular, RRAM-based FPGAs operating in the near-Vt regime demonstrate a 5x power improvement without delay overhead as compared to optimized SRAM-based FPGA operating at nominal working voltage.

Ternary Content Addressable Memory (TCAM) is widely used in network infrastructure for various search functions. There has been a growing interest in implementing TCAM using reconfigurable hardware such as Field Programmable Gate Array (FPGA). Most of existing FPGA-based TCAM designs are based on brute-force implementations, which result in inefficient on-chip resource usage. As a result, existing designs support only a small TCAM size even with large FPGA devices. They also suffer from significant throughput degradation in implementing a large TCAM, mainly caused by deep priority encoding. This paper presents a scalable random access memory (RAM)-based TCAM architecture aiming for efficient implementation on state-of-the-art FPGAs. We give a formal study on RAM-based TCAM to unveil the ideas and the algorithms behind it. To conquer the timing challenge, we propose a modular architecture consisting of arrays of small-size RAM-based TCAM units. After decoupling the update logic from each unit, the modular architecture allows us to share each update engine among multiple units. This leads to resource saving. The capability of explicit range matching is also offered to avoid range-to-ternary conversion for search functions that require range matching. Implementation on a Xilinx Virtex 7 FPGA shows that our design can support a large TCAM of up to 2.4 Mbits while sustaining high throughput of 150 million packets per second. The resource usage scales linearly with the TCAM size. The architecture is configurable, allowing various performance trade-offs to be exploited. To the best of our knowledge, this is the first FPGA design that implements a TCAM larger than 1 Mbits.

In current CMOS nanometer technologies, aging effects may appear after relatively short operating times, compared to the expected lifetime of circuits. Therefore, there is an increasing need for on-chip aging monitoring, especially in high-performance, safety critical systems. This paper presents a programmable aging sensor that can be embedded in field-programmable gate array (FPGA)-based designs, using standard resources available in those devices and with minimal impact on the standard FPGA design flow. Given the limited amount of resources required by the sensor, it can be instantiated not only in the critical paths of a circuit, but also in those that may be identified to be more likely affected by aging effects. Experimental results, obtained in circuits of increasing complexity (where several sensors need to be used), are presented and discussed, demonstrating the good performance of the proposed sensor, as well as its low cost in terms of area overhead and power consumption. Results of aging experiments based on the standard US MIL-STD-883 Method 1015.50 "Burn-In Test" are also reported, demonstrating that the effect of aging on the sensor is negligible compared to that on the circuit under test, which is a key point for practical applicability. The proposed approach provides a novel and efficient solution to the specific FPGA design problems in this context, which are different from those addressed in application-specific integrated circuit design.