Design and test of signal processing hardware for two-dimensional phased array digital multi-beam system

In order to fulfil real time signal processing tasks such as clutter rejection, moving target detection (MTD) and constant false alarm rate (CFAR) control in airborne radar, an airborne radar parallel signal processing system (ARPS2) is proposed with DSP chips as its kernel processing nodes. The DSP chips are used with parallel architecture. Each node has its private input and output memory. It adopts several parallel techniques, such as parallel storage, parallel processing, parallel code loading and parallel data organization to achieve high efficiency. It has a simple structure, excellent flexibility and easiness in developing. ARPS2 is going to be applied to an airborne radar. It can also be applied to perform high-speed real time signal processing algorithms in other kinds of radar.

Cylindrical phased array radar has an important role in low-altitude target surveillance, and signal processing is one of the important component modules of the radar system. Cylindrical radar as one kind of phased-array radar has the characteristics of full azimuth range of multi beam and huge data which makes high demands of signal processing. FPGA occupies an important position in radar signal processing because of its characteristics of high-speed and real-time. In this paper, signal processing scheme based on Xilinx's FPGA Kintex-7 and multi-core digital signal processor (DSP) is proposed, which mainly implements functions such as data reception, pulse compression, and moving target detection (MTD) processing etc. By comparing the actual results with the matlab simulation results, it is shown that this scheme has a good performance in stablility with fast processing speed. Moreover, it has obvious advantages in the design and provides great value for engineering.

Traditional image matching algorithm based on gray correlation provides accurate results but it is time-consuming because of large amount of calculation. An improved gray correlation based image matching algorithm based on multi-core DSP is proposed to speed up the matching velocity with the acceptable margin of errors. With the development of portable embedded image processer, especially the multi-core DSPs for parallel computing to speed up the process, these image matching algorithms need to be transplanted to these embedded system. Experiments based on CPU in the form of Visual C++6.0 application program and multi-core Digital Signal Processor(DSP) verify the effectiveness of the algorithm, making it applicable to embedded image processing system with a multi-core DSP.

Current legislation in European countries, as well as in other parts of the world, is putting stricter limits on pollutant emissions from road vehicles. This issue, in conjunction with the increase awareness of consumer for the environmental problems, will require the development of new clean propulsion systems in disruption with the current mobility solutions based on internal combustion engine. Electric, hybrid and fuel-cells vehicles (Chan, 2007) are now recognized as an indispensable mean to meet the challenges associated with sustainable mobility of people and goods. In this paradigm shift, the electric motor (EM) will assume a key role in the propulsion of future vehicles and, unlike vehicles based on internal combustion engines, the high energy and power densities will facilitate the development of new powertrains configurations. In particular, multi-motor configurations, where several EMs are allocated to each driven wheel of the vehicle, represent an attractive configuration for electric vehicles (EVs), due to the independent wheel torque control and the elimination of somemechanical systems, like the differential. These features, allied with the fast dynamics of EMs, are being explored to increase the vehicle maneuverability and safety (Geng et al., 2009) and improve the performance of the EV traction system (Hori, 2004). To cope with this rise in functional and computational complexity that current (and future) EVs require, in this work we explore the new Field-programmable Gate Array (FPGA) platform to address the powertrain control, i.e. involving the electric motor and the power converters control, of multi-motor EVs. In the past two decades, motor control applications have been dominated by software based solutions implemented in DSPs (Digital Signal Processors), due to the low cost and ease of programming (Cecati, 1999). However, these DSP solutions are facing increasing difficulties to respond to the ever-increasing computational, functional and timing specifications that modern industrial and vehicular applications require (Monmasson & Cirstea, 2007). For instance, when single-coreDSP based solutions needs to incorporate complex and time-critical functions, e.g. multi-motor control, the sequential processing of this approach decrease the controller bandwidth (see Fig. 1), which may compromise the application timing specification. Multi-core DSPs are a possible alternative to address this concern, but they also add costs and interconnection complexity. Consequently, in the last years, FPGAs received an increased interest by the academy and industry as an option to offload time-critical tasks from the DSPs (Lopez et al., 2008; Rahul et al., 2007; Ying-Yu & Hau-Jean, 1997), or even replace the DSPs control platform by a System on Chip (SOC) based on FPGAs (Idkhajine et al., 2009). 7

Implantable systems that monitor biological signals require increasingly complex digital signal processing (DSP) electronics for real-time in-situ analysis and compression of the recorded signals. While it is well-known that such signal processing hardware needs to be implemented under tight area and power constraints for small footprint and increased battery-life, new design requirements emerge with their increasing complexity. Use of nanoscale technology shows tremendous benefits in implementing these advanced circuits due to dramatic improvement in integration density and power dissipation per operation. However, it also brings in new challenges such as reliability and high leakage power. Besides, programmability of the device and security of the recorded information are desirable features, which need to be considered during the design of such systems. Programmability is important to adapt to individual subjects as well as to the temporal fluctuations in subject condition. On the other hand, information security is rapidly becoming an important design parameter since the recorded signal often needs to be transmitted outside the body through wireless channels. In this paper, we analyze the emerging issues associated with the design of the DSP unit in an implantable system. We note that conventional design solutions may not be attractive for such systems. However, novel algorithm-architecture-circuit co-design solutions, which leverage on the nature of the signal processing algorithms can be effective to realize ultra low-power, robust, programmable and secure hardware for on-chip realtime signal processing in implantable systems.

On the basis of the characteristic analysis of data transmission and interconnection interface in complicated radar real-time signal processing system, a multi-rate data exchange system based on large-scale FPGA is designed. Then the structure and composition of this system are described in detail. The system has the characteristics of standardization, modularization and scalability. And through the implementation and application in an airborne SAR signal processing system, the universality and flexibility of this system were proved. (4 pages)

A DSP-based all-purpose radar parallel signal processing system (RPSPS) with high-speed real-time signal processing is implemented to fulfil the all-purpose radar system reconfiguration. High performance DSP chips are used as the kernel processing nodes. By means of local shared memory, a global distributed memory parallel system and the pipelined dataflow method, it can perform absolutely parallel data processing of multi DSP. The finished system is simple in architecture, flexible in scale. The reconfiguration of this system through the embedded computer makes it possible to implement the different signal processing tasks of other radar systems without changing the system hardware.

Device-to-device (D2D) communication can offload the mobile network and increases the spectral efficiency, which has become a hot topic in wireless communication. Many research results have been proposed to solve the key problems, such as interference and resource allocation in D2D communication. This paper is based on a D2D prototype development project, discussing a scheme to implement physical layer of D2D communication by multi-Core digital signal processing (DSP). Performance verifications prove that the DSP subsystem and the entire D2D prototype system have reached the required functions of proximity discovery and data transmission.

This paper addresses the efficient implementation of a robust gradient-based optical flow model in a low-power platform based on a multi-core digital signal processor (DSP). The aim of this work was to carry out a feasibility study on the use of these devices in autonomous systems such as robot navigation, biomedical assistance, or tracking, with not only power restrictions but also real-time requirements. We consider the C6678 DSP from Texas Instruments (Dallas, TX, USA) as the target platform of our implementation. The interest of this research is particularly relevant in optical flow scope because this system can be considered as an alternative solution for mid-range video resolutions when a combination of in-processor parallelism with optimizations such as efficient memory-hierarchy exploitation and multi-processor parallelization are applied.

WIOBSS is a new kind of the full phase-parameter, digital Ionospheric Oblique Backscattering Sounding System that has been developed by Ionosphere Lab in Wuhan University for Ionospheric monitoring and research. It bases on the principle of pseudo-random noise (PN) phase modulated pulse compression and employs long coded pulses, a high PRF, and coherent integration to achieve adequate sensitivity while operating at lower power (less than 800 watts). By means of WIOBSS system, we can get a lot of useful information, such as the dynamic change character of the Ionosphere, Doppler frequency shift and spread about the channel. According to the character of WIOBSS, this paper provides a discussion on its architecture design in detail. The experimental results demonstrate that this architecture is computer controlled by software, designed as VXI bus-based modelled radar digital signal processing system, and its flexibility, versatility, upgrading can fully satisfy the demands of WIOBSS.

An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devising a hybrid CSA. In the proposed adder, CSA uses CLAA technology to generate the carry bits for each sum bit, which are then used to select the respective multiplexer (MUX) which adds the carry bit to the sum accordingly. The proposed adder has been synthesized with bulk 40 nm standard CMOS library on Synopsys Design Compiler. Analysis has indicated the superiority of proposed adder over CLAA and CSA. As compared to CSA and CLAA, the proposed Carry Select Ahead Adder (CSAA) provides shorter average path and a simpler hardware. This has led to faster processing speed by increasing the complexity of circuit on the chip. The proposed adder finds its applications in various Arithmetic and Logic Units (ALU) of CPUs for faster arithmetic results. Keywords—Carry Look Ahead Adder (CLAA), Carry Select Adder (CSA), Multiplexer (MUX), Carry Select Ahead Adder (CSAA), Arithmetic and Logic Unit (ALU).

The entry of digital signal processors in modern control systems not only allows for extended diagnostics compared to analog systems but also for sophisticated and tricky extensions of the control algorithms. With modern DSP- and FPGA-technology, the processing speed of digital systems is no longer inferior to analog systems in many applications. A higher degree of digitalization leads to an increased complexity of the systems and hence to higher requirements on their operators. The focus of research and development in the field of high frequency control has changed in the last few years and moved towards the direction of software development and complexity management. In the presented thesis, a frame for an automation concept of modern high frequency control systems is developed. The developed automation is based on the concept of finite state machines (FSM), which is established in industry for years. A flexible framework was developed, in which procedures communicate using standardized interfaces and can be exchanged easily. With that, the developer of high frequency control components as well as the operator on shift shall be empowered to improve and adapt the automation to changed conditions without special programming skills required. Along the automation concept a number of algorithms addressing various problems were developed which satisfy the needs of modern high frequency control systems. Among the developed and successfully tested algorithms are the calibration of incident and reflected wave of resonators without antennas, the fast adaptive compensation of repetitive errors, the robust estimation of the phase advance in the control loop and the latency adjustment for the rejection of instabilities caused by passband modes. During the development of the resonator theory, high value was set on the usability of the equation in algorithms for high frequency control. The usage of the common nomenclature of control theory emphasizes the underlying mathematical structures of the equations. Several physical limitations and requirements, for example the limits of the vector sum calibration, were newly and adequately calculated based on the developed theory. The linear accelerator of the Free-Electron Laser in Hamburg (FLASH) served as the main platform for testing of the algorithms and concepts. The developed automation, in particular the flexible and transparent framework and methods for the reduction of the complexity of the various communication channels (quantization) is not only suited for high fequency control but also for other aspects of an accelerator and beyond.

<p><span>Scene segmentation is an essential step in a wide range of video processing applications, for instance, object recognition and tracking. The Gaussian mixture model (GMM) for background subtraction (BS) has gained widespread usage in scene segmentation, despite its known computational intensity. To tackle this challenge, we propose a practical solution to accelerate processing through a parallel implementation on an embedded multicore platform. In this paper, we present an improved automated parallel implementation of the GMM algorithm using the Orphan directive provided by open multiprocessing (OpenMP). Experimental assessments conducted on the eight cores of the C6678 digital signal processor (DSP) demonstrate significant advancements in parallel efficiency, particularly when handling high-resolution frames, including high-definition (HD) and full-HD resolutions. The achieved parallel efficiency surpasses the results obtained with classical OpenMP scheduling modes, encompassing dynamic, static, and guided approaches. Specifically, the parallel efficiency reaches approximately 82% for full-HD resolution frames and, 99.3% for low-resolution frames, respectively.</span></p>

Today, DAW (Digital Audio Workstation) software lies at the heart of music production and has become an indispensable part of the industry. With the advancement of technology, music production is no longer confined to large studios but has also become accessible to individual users. Now, recording, mixing, and mastering processes can be carried out in a home environment using computer-based systems, without the need for expensive equipment. This fully digital workflow is referred to as "in-the-box" production. Technological developments have enabled individuals to produce music at a professional level in home studios, leading to the emergence of digital alternatives to analog devices. Digital processors have begun to replace analog equipment due to their cost-effectiveness and practicality. This study examines the differences between digital signal processors and analog devices in terms of usage, application areas, and sound processing methods. The research aims to compare digital and analog signal processors, particularly focusing on their processing methods, speed, flexibility, quality, and impact on sound. Based on the findings, it is concluded that digital signal processors, which are increasingly replacing analog processors in the music industry, do not possess the same characteristics as their analog counterparts.

Many curricula include separate classes in both digital signal processing (DSP) theory and very high-speed integrated circuit hardware description language (VHDL) modeling; however, there are few opportunities given to students to combine these two skills into a working knowledge of DSP hardware design. A pedagogical framework has been developed whereby students can leverage their previous knowledge of DSP theory and VHDL hardware design techniques to design, simulate, synthesize, and test digital signal processing systems. The synthesized hardware is implemented on field-programmable gate arrays (FPGAs), which provide a fast and cost-effective way of prototyping hardware systems in a laboratory environment. This framework allows students to expand their previous knowledge into a more complete understanding of the entire design process from specification and simulation through synthesis and verification. Students are exposed to different aspects of signal processing design, including finite precision, parallel implementation, and implementation cost tradeoffs.