Design of 32-bit Processor for Embedded Systems

This paper presents the design and implementation of a pipelined 9-bit RISC Processor. The various blocks include the Fetch, Decode, Execute and Store result to implement 4 stage pipelining. Harvard Architecture is used which has distinct program memory space and data memory space. The only load and store is used to communicate with data memory. RISC using pipeline makes CPI as 1 and improves speed of execution. Verilog Language is used for coding purpose. The proposed architecture is then simulated using Modelsim. Reduced Instruction Set Computers (RISCs) are now use for all type of computational tasks. In the area of scientific computing, RISC workstations are being increasingly used for compute task such as DSP, DIP etc. RISC concepts help to achieve given levels of performance at significantly lower cost than other systems. Pipelined RISC improves speed and cost effectiveness over the ease of hardware description language programming and conservation of memory and RISC based designs will continue to grow in speed and ability. The main features of RISC processor are the instruction set can be hardwired to speed instruction execution. In the present work, the design of a 4-bit data width Reduced Instruction Set Computer (RISC) processor is presented. It has a complete instruction set, program and data memories, general purpose registers and a simple Arithmetical Logical Unit (ALU) for basic operations. In this design, most instructions are of uniform length and similar structure, arithmetic operations are restricted to CPU registers and only separate load and store instructions access memory. The architecture supports 8 instructions to support Arithmetic, Logical, Shifting, and load -store operations. Verilog HDL has evolved as a standard hardware description language. A hardware descriptive language is a language used to describe a digital system. HDL's allows the design to be simulated earlier in the design cycle in order to correct errors or experiment with different architectures. Designs described in HDL are technology- independent, easy to design and debug, and are usually more readable than schematics, particularly for large circuits. More recently Verilog is used as an input for synthesis programs which will generate a gate-level description for the circuit. The simulator which is used for the language is Xilinx ISE and Modelsim. Verilog is capable of describing simple behaviour. Machine cycle instructions allow the processor to handle several instructions at the same time. The processor can work at a high clock frequency and thus yields higher speed. This paper is about design of a simple RISC processor and synthesizing it. The RISC architecture follows single-cycle instruction execution.

Hardware software co-design plays a crucial part in the embedded processor development especially with the current advancement of reconfigurable platforms. The reconfigurability features offered by platforms such as Field Programmable Gate Array (FPGA) has permitted the modification of the internal processor architecture with lower cost and higher performance. While the hardware architecture could be changed through various methods, the modifications need to be complemented with a compatible assembler that suits the amended architecture. This paper presents a two-pass assembler design technique that adapts to any instruction set architecture (ISA) modifications being applied on a reconfigurable processor. A Reduced Instruction Set Computer (RISC) processor core, which is described in Verilog Hardware Description Language (HDL), is used as the testing platform whereby its ISA is expanded to include new instruction sets. The assembler is developed based on two-pass approach and the assembling process would generate a coefficient file that is used as initialization files during the FPGA implementation of the processor core. The assemblers have been successfully developed with correct output format and verified during the FPGA implementation using Xilinx Spartan-3AN board.

Reduced Instruction Set Computer Five (RISC-V) is an open-source processor instruction set architecture which is rapidly gaining popularity in space applications. Not only can this architecture be implemented in standalone application specific integrated circuit (ASIC) hardware processors, but can be configured within field-programmable gate array (FPGA) fabrics. This paper will discuss the benefits and challenges of using RISC-V soft-cores within radiation-tolerant FPGAs for embedded space applications. Spacecraft are limited by size, weight, power, and cost (SWAP-C), and most rely on both FPGAs and discrete microprocessors to meet onboard processing needs. With advances in capacity for radiation-hardened FPGAs, it is now feasible to implement an advanced soft-core microprocessor (or even multiple cores) within the FPGA itself. This has potential to reduce part count and simplify designs greatly, make efficient use of spare FPGA capacity, and reduce the overall SWAP-C of spaceflight computers. The research team tested the latest RISC-V FPGA offerings from Microchip (product name Mi-V) and CAES (product name NOEL-V). The performance of these processor implementations was measured on a standard benchmark suite across multiple operating systems on evaluation hardware. This paper describes our test methodology, analysis, and conclusions.

In this article, we implemented a fully digital Coincidence Doppler Broadening (CDB) spectrometer consisting of two HPGe detectors, a fully digital processing and acquisition board, and a dedicated software system. The Field Programmable Gate Array (FPGA) on the board extracts energy and time stamp of digitized pulses from HPGe detectors, and communicates with the dedicated software by which the single channel spectrums and 2D coincidence spectrum were produced. We designed an instruction set dedicated to the CDB Spectrometer and the controller module in FPGA so that the FPGA subsystem is fully controllable and configurable. The trapezoidal pulse shaping algorithm was implemented in FPGA whose arguments are all configurable through the dedicated software by the instruction set. We examined the long-term stability of the spectrometer by 511 keV peak position of both channels. The 2D Gaussian fitting is performed on coincidence spectrum by the software to correct the peak drift of both channels. The results show that this method effectively improves the Doppler-broadened spectrum, by which the peak-to-background ratio increases from 7.0 × 105 to 1.9 × 106.

A dual-issue 32-bit RISC-V processor is designed and reported. In order to evaluate the performance of the dual-issue processor, a single-issue processor based on the open source RISC-V instruction set architecture is first designed for reference and it is also the base of the dual-issue processor. The single-issue reference processor, which has a 5-stage pipeline, supports base integer instruction set, integer multiplication and division and compressed instructions, has passed the corresponding functional and compliance tests. The dual-issue processor extends the pipeline to dual-issue and introduces additional processing to solve data hazards in the pipeline. The evaluated result of the dual-issue processor shows that it has significant performance improvement than the single-issue processor.

Fast Fourier transformation (FFT), a kernel data processing task in communication systems, has been studied intensively for efficient software and hardware implementations. Nowadays, various orthogonal frequency division multiplexing (OFDM)-based wireless communication standards have raised more stringent requirements on both throughput and flexibility for FFT computation. Application-specific instruction set processor (ASIP) has emerged as a promising solution to meet these requirements. This paper presents a novel hierarchical design of an ASIP tailored for FFT. We reconstruct the FFT computation flow into a scalable array structure based on an 8-point butterfly unit (BU). The array structure can easily expand along both the horizontal and vertical dimensions for any-point FFT computation. We incorporate custom register files to reduce memory access and derive a regular data addressing rule accordingly. With the microarchitecture modifications, we extend the instruction set architecture (ISA) with new instructions to accelerate FFT operations. An FFT ASIP is implemented on Tensilica's reconfigurable processor platform. Our FFT ASIP achieves the data throughput of 405.7 Mb/s for 1 K-point FFT, which attains UWB-OFDM specifications. The area of our custom processor is 147 kilo gates and the total processor power consumption is 60.7 mW, which are acceptable compared to several other designs such as application specific integrated circuit, digital signal processing, field-programmable gate array, and other ASIP implementations. We also extend the implementation for up to 8 K-point FFTs, with degraded performance but still meeting the requirements of those communications standards that demand large-size FFT computations.

Reconfigurable computing provides a paradigm to create intelligent systems different from the classic software computing approach. Instead of using a processor with an instruction set, a full stack of middleware, and an application program running on top, the field-programmable gate arrays (FPGAs) integrate a cell set that can be configured in different ways. A few vendors have dominated this market with their proprietary tools, hardware devices, and boards, resulting in fragmented ecosystems with few standards and little interoperation. However, a new and complete toolchain for FPGAs with its associated open tools has recently emerged from the open-source community. Robotics is an expanding application field that may definitely benefit from this revolution, as fast speed and low power consumption are usual requirements. This paper hypothesizes that basic reactive robot behaviors may be easily designed following the reconfigurable computing approach and the state-of-the-art open FPGA toolchain. They provide new abstractions such as circuit blocks and wires for building intelligent robots. Visual programming and block libraries make such development painless and reliable. As experimental validation, two reactive behaviors have been created in a real robot involving common sensors, actuators, and in-between logic. They have been also implemented using classic software programming for comparison purposes. Results are discussed and show that the development of reactive robot behaviors using reconfigurable computing and open tools is feasible, also achieving a high degree of simplicity and reusability, and benefiting from FPGAs’ low power consumption and time-critical responsiveness.

Chapter 14 - Embedded Processing Cores

Due to the trend towards low power operation, as in autonomous systems where power constraints are very high, sensors are increasingly being required to dissipate very low power (few microwatts). In this paper, a low-power version of a smart temperature sensor in 0.7 mum CMOS technology is presented. Based on accuracy requirements, a minimum biasing current Ibias for the sensor's bipolar core is determined. Measurement results for Ibias = 250 nA and CS = 1.25 pF (ADC sampling capacitor) are shown. An inaccuracy below plusmn0.15degC from -55degC to 125degC is achievable with a two-point calibration.

Compared with the four-phase optical structure, the grating encoder based on two-phase optical structure reduces the number of optical devices used in the system and makes the system more compact. Due to the high requirements for realtime and parallel processing of algorithm solution, the powerful parallel computing ability of Field Programmable Gate Array (FPGA) and customized hardware acceleration algorithm are needed to improve the real-time performance. In the previous research, the displacement signal generated by the grating encoder can be input into the FPGA through analog to digital converter (ADC) sampling, and then complete self-designed filter filtering, phase correction and displacement solution. In this paper, further, the ADC sampling rate adjustable interface is added to the FPGA, the global signal and the dc offset remove algorithm is added, and the displacement solution results in the form of fixed-point number are output to the host computer through the MicroBlaze (MB) soft core. MB core can realize process control and interface conversion on FPGA, and use a small amount of logic resources to replace the functions of MCU and DSP of traditional embedded measurement system, so as to further improve the integration of the instrument. A series of experiments are carried out on the two-phase FPGA platform. ADC sampling rate is 200ksps, 8-Channel synchronous parallel sampling, FPGA system clock frequency is 200MHz. The linear displacement table is set to drive the measurement grating at different displacement speeds, and the total stroke is set to 10mm. The FPGA real-time displacement solution platform is tested. The experimental results show that FPGA obtains accurate displacement solution results under different speed tests. In the test of 2 mm/s, the maximum cumulative displacement measurement error is 5um, which shows the real-time performance and accurate displacement solution performance of FPGA platform.

With regard to the application requirement of the Field Programmable Gate Array(FPGA)in embedded system,a data communication interface between the FPGA and ARM was designed and implemented.Based on the implementation of the FPGA device driver in the embedded Linux 2.6,the detailed discussion was given:the achievement of the operation of FPGA through the memory mapping mechanism and the improvement on the system efficiency through the blocking operation.Referring to the related data structures and functions of Linux2.6.15,a device driver was programmed and tested for the FPGA device.This FPGA interface driver,which had been applied and tested for a long time,ran steadily in the whole system.

Frequency Modulated Continuous Wave (FMCW) radar has extensive areas of application for both civil and military use due to its good performance and detection capabilities. FMCW radar signal processing is based on two main modules; Moving Target Indicator (MTI) and Two-Dimensional Fast Fourier Transform (2D-FFT). Detection performance of FMCW radar is degraded due to the attenuation of the signals come from slowly moving targets with small visible Doppler frequencies. Also, the detection degradation of the targets whose beat frequency do not lie on the FFT grids. These problems have been introduced and overcome. In this paper, a complete design and implementation of LFMCW radar signal processor incorporating the solution of these problems are introduced on a field programmable gate array (FPGA) to facilitate real time processing. Simulation and experimental measurement are found to be identical illustrating the capability of the applied methods. The hardware implementation includes generation of the digital sawtooth waveform, Dechirping process,2D_FFT processing, Windowing, MTI, Single Delay Line Integrator and off pin filter.

Laser speckle imaging (LSI) is a noninvasive and full-field optical imaging technique which produces two-dimensional blood flow maps of tissues from the raw laser speckle images captured by a CCD camera without scanning. We present a hardware-friendly algorithm for the real-time processing of laser speckle imaging. The algorithm is developed and optimized specifically for LSI processing in the field programmable gate array (FPGA). Based on this algorithm, we designed a dedicated hardware processor for real-time LSI in FPGA. The pipeline processing scheme and parallel computing architecture are introduced into the design of this LSI hardware processor. When the LSI hardware processor is implemented in the FPGA running at the maximum frequency of 130 MHz, up to 85 raw images with the resolution of 640×480 pixels can be processed per second. Meanwhile, we also present a system on chip (SOC) solution for LSI processing by integrating the CCD controller, memory controller, LSI hardware processor, and LCD display controller into a single FPGA chip. This SOC solution also can be used to produce an application specific integrated circuit for LSI processing.

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