Design of an FPGA-based Real-Time Simulator for electrical system

Field Programmable Gate Array (FPGA) devices are coming very strongly in the digital hardware systems due to the availability of ready to use resources, parallel logic operations and reconfigurable designs. The usage of FPGA systems in real time domain is also a very fruitful proposition as the FPGA devices are coming with processing cores for Real Time data processing. In a complex system scenario involving a large amount of processing tasks, there is a requirement of building the system using multiple FPGA devices. To make this possible we have to establish a real time data communication between the FPGA devices and to make it even better we have to apply data encryption techniques for making this communication secured.In this paper we demonstrate the design and implementation of a 32-bit RSA algorithms by developing suitable Hardware and Software design on Xilinx Spartan- 3E (XC3S500E-FG320) device, the implementation has been tested successfully for real time serial data communication between multiple FPGA devices using the RS232 serial interface. This development work is also useful for the embedded applications, which requires on board execution of security algorithms. The system is optimized in terms of execution speed and also has been verified using real time debugging tools.

This article presents a critical literature review on the security aspects of field-programmable gate array (FPGA) devices. FPGA devices present unique challenges to cybersecurity through their reconfigurable nature. The article also pays special attention to emerging system-on-chip (SoC) FPGA devices that incorporate a hard processing system (HPS) on the same die as the FPGA logic. While this incorporation reduces the need for vulnerable external signals, the HPS in SoC FPGA devices adds a level of complexity that is not present for stand-alone FPGA devices. This added complexity necessarily hands over the task of securing the device to developers. Even with standard security features in place, the HPS might still have unhindered access to the FPGA logic. A single software flaw could open up a breach that might allow an attacker to extract the FPGA’s configuration data. A robust cybersecurity strategy is thus required for developers. As such, this work aims to provide the groundwork to build a solid threat-based cybersecurity design strategy that is specially adapted to SoC FPGA devices.

Component-aging is unavoidable in legacy systems. Although re-designing the system typically results in a high cost, the need to replace aged components for legacy systems is an urgent priority. Unfortunately, the aged components are likely to be obsolete and not available on the current market. Obsolete component replacement with field-programmable gate array (FPGA) devices is emerging as a feasible option to extend the lifetime of legacy systems. While replacing the aged component, we traditionally only focus on matching the functionality and neglect the potential security threats from FPGA replacement. However, recent literature demonstrates that FPGA devices may contain hardware Trojans, which are induced during FPGA device fabrication or bitstream generation time. To prevent the Trojans on FPGA from receiving external inputs or leaking sensitive information, we propose a Runtime Pin Grounding (RPG) scheme to ground the unused pins and check the pin status at every clock cycle. Furthermore, we exploit the principle of moving target defense (MTD) and propose a hardware MTD (HMTD) method. In our method, the aged obsolete unit is replicated to multiple copies in the FPGA device, and two of the replicas are randomly selected for output comparison and thus Trojan detection. We successfully implemented the proposed RPG and HMTD methods on a Nexys-3 FPGA board. Our case study shows that the proposed RPG scheme increases the FPGA utilization rate by less than 0.1%. On average, our HMTD method reduces the hardware Trojan bypass rate by 61% over the existing method.

The literature review explores the evolution and advancements in the implementation of latency-based solvers for real-time simulation of power electronic systems using field-programmable gate arrays (FPGAs).The journey begins with Dr. Johnson, who highlights the exceptional capability of FPGAs to outperform traditional general-purpose processors in floating-point throughput for power flow computations.[1] This foundational work sets the stage for subsequent research that delves deeper into the acceleration of various computational tasks using FPGA technology.As the field continues to mature, new methodologies and algorithms are developed to harness the full potential of FPGAs.These innovations aim to not only improve the performance of power electronic simulations, but also to enhance the flexibility and reconfigurability of the systems.Researchers are exploring novel approaches such as adaptive solvers, where the latency of the system dynamically adjusts based on the complexity of the simulation.[2] This adaptive nature allows for efficient resource allocation and utilization in real-time applications, leading to improved overall system performance.Furthermore, advancements in FPGA architecture and design techniques enable the integration of multiple solvers on a single chip, catering to the increasing demand for multi-domain simulations.This integration paves the way for seamless co-simulation of diverse power electronic systems, including converters, inverters, and motor drives.Additionally, the emergence of high-level synthesis tools simplifies the development process, making it more accessible to researchers and practitioners alike.[3] These tools enable the conversion of high-level hardware description languages into FPGA-specific designs, alleviating the need for manual low-level coding.Moreover, the availability of FPGA development boards and development kits provides a testing ground for prototype implementations, allowing researchers to evaluate their designs in a real-world scenario.[1] In conclusion, the literature review highlights the evolutionary journey of latency-based solvers for real-time power electronic simulations using FPGAs.From the initial groundbreaking work to the current state-of-the-art advancements, researchers have continuously pushed the boundaries to achieve higher performance and accuracy.With ongoing research and innovation, the field is poised for further growth and development, promising even more efficient and versatile solutions for real-time power electronic simulations.[4] [5] build on this foundation by addressing the parallelization of the sparse Matrix-Solve phase in SPICE applications.Their findings indicate that reduced-precision floating-point datapaths can significantly enhance performance, achieving speedups of 2-18 times over single-core microprocessor implementations.This article emphasizes the importance of exploiting parallelism and optimizing resource usage in FPGA designs.The authors present an FPGA-based framework that effectively tackles and addresses the inherent challenges associated with simulating intricate physical phenomena utilizing unstructured spatial discretization.This innovative and pioneering approach significantly enhances data locality and memory access patterns, thereby showcasing a remarkable and astonishing 90 times speedup as compared to high-performance microprocessors.[1] The demonstrated outcomes and results of this work serve to underscore and emphasize the critical significance of efficient and effective memory management when harnessing and leveraging the immense computational power offered by FPGAs.This research proves to be a groundbreaking and pivotal advancement in the field, with far-reaching implications and potential for further exploration and application in diverse areas of study.[6] Introduce FPGA-SPICE, which is a state-of-the-art simulation-based power estimation framework that perfectly integrates seamlessly with cutting-edge architecture exploration tools.

Building the machines that advance scientific knowledge is one of the most significant challenges of our time. So-called Big Science instruments are unique; the expertise required to build them is multidisciplinary, and few countries can build and maintain them. Since resources and budgets are not unlimited, these require efficient solutions. Big Science machines take a decade to plan, a decade to build, and at least a decade to operate. One such machine is the largest fusion reactor project, ITER, which promises to be the next step in fusion research and has a big challenge in system integration. To mitigate the integration effort, ITER has invested in standardization, both in software and hardware, introducing standard instrumentation software named Nominal Device Support (NDSv3); Micro Telecommunication Computing Architecture (MTCA) as the long-term hardware standard choice, and EPICS as a general-purpose distributed control system. These control systems are essential in the management of the facility. They provide functions such as communication protocols, process management, monitoring, alarms, and human-machine interfaces. But also, more advanced access to databases or data acquisition systems. The latter is typically managed by a Field Programmable Gate Array (FPGA), of which facilities can easily have thousands of these FPGAs managing millions of signals within the control system environment. Nevertheless, these FPGA data acquisition (DAQ) systems continue to be labor-intensive. Standardized, modular, and open-source frameworks have been proposed to solve this problem, however, the FPGA programming expertise requirement remained. This thesis proposes a complete technology stack that considers these DAQ systems from the control system to the hardware. It provides a methodology using the Open Computing Language (OpenCL) to reduce the FPGA programming effort. The FPGA devices are programmed using C/C++-like environments, which are much simpler than traditional Hardware Description Languages (HDLs). The software, named IRIO-OpenCL, is written in C++ following ITER's NDSv3 model, which abstracts and generalizes the development of software device drivers and simplifies the interface to EPICS. IRIO-OpenCL is specifically designed to simplify the integration of intelligent instrumentation systems, allowing the integration of algorithms into the FPGA without modifying large parts of the supporting library. The MTCA standard was chosen to maintain modularity. The chassis backplane connects to the devices via Ethernet and PCIe, enabling standard communications. The Advanced Mezzanine Card is the typical MTCA FPGA-based DAQ carrier board. It connects the FPGA to the chassis backplane and typically provides FPGA Mezzanine Connectors (FMCs) for plugging in analog-to-digital (ADC) carrier boards. An ADC connected via the FMC interface samples the analog signals passed to the OpenCL processing kernels. Using OpenCL, the FPGA kernels communicate with the host machine in a standardized way. To demonstrate the applicability of this methodology, reference problems were selected from the literature and implemented, both with traditional and deep learning (DL) solutions. The methodology elaborates on connecting the OpenCL kernels for any use case, and the results show examples of kernel sets. The neutron flux measurement problem is solved at 1GS/s in real time using pulse counting and Campbell techniques, using 40% of the target Arria10 FPGA. The DL application example is based on a neutron/gamma discrimination neural network (NN) that achieves a classification rate of up to 1.3 MEvents/s using less than 25% of the target resource. RESUMEN Construir máquinas que avancen el conocimiento científico es uno de los desafíos más significativos de nuestro tiempo. Los instrumentos de la llamada Big Science son únicos; las competencias requeridas para su construcción son multidisciplinares, y pocos países pueden construirlos y mantenerlos. Dado que los recursos y presupuestos no son ilimitados, estos requieren soluciones eficientes. Las máquinas de Gran Ciencia tardan una década en planificarse, una década en construirse y al menos una década en operarse. Una de estas máquinas es el proyecto del reactor de fusión más grande, ITER, que promete ser el siguiente paso en la investigación de fusión y presenta un gran desafío en la integración de sistemas. Para mitigar el esfuerzo de integración, ITER ha invertido en estandarización, tanto en software como en hardware, introduciendo un software de instrumentación estándar llamado Nominal Device Support v3 (NDSv3); Micro Telecommunication Computing Architecture (MTCA) como la elección estándar de hardware a largo plazo, y EPICS como un sistema de control distribuido de propósito general. Estos sistemas de control son esenciales en la gestión de la instalación ya que proporcionan funciones como protocolos de comunicación, gestión de procesos, monitorización, alarmas e interfaces de usuario, además de acceso avanzado a bases de datos o sistemas de adquisición de datos. Este último es típicamente gestionado por un Field Programmable Gate Array (FPGA), de los cuales las instalaciones pueden tener fácilmente miles de unidades gestionando millones de señales dentro del entorno del sistema de control. Estos sistemas de adquisición de datos (DAQ) con FPGA siguen requiriendo programación experta y laboriosa. Se han propuesto marcos estandarizados, modulares y de código abierto para resolver este problema, sin embargo, la necesidad de experiencia en programación FPGA no se ha podido eludir. Esta tesis propone una pila de tecnologías que considera estos sistemas DAQ desde el sistema de control hasta el hardware. Proporciona una metodología utilizando el Open Computing Language (OpenCL) para reducir el esfuerzo de programación FPGA. Los dispositivos FPGA se programan utilizando entornos similares a C/C++, que son mucho más simples que los Lenguajes de Descripción de Hardware (HDL) tradicionales. El software, llamado IRIO-OpenCL, está escrito en C++ siguiendo el modelo de NDSv3 de ITER, que abstrae y generaliza el desarrollo de controladores de dispositivos de software y simplifica la interfaz con EPICS. IRIO-OpenCL está específicamente diseñado para simplificar la integración de sistemas de instrumentación inteligentes, permitiendo la integración de algoritmos en el FPGA sin modificar grandes partes de la biblioteca de soporte. El estándar MTCA fue elegido para mantener la modularidad. El backplane del chasis se conecta a los dispositivos a través de Ethernet y PCIe, habilitando comunicaciones estándar. La Advanced Mezzanine Card es la placa portadora DAQ FPGA típica de MTCA, que conecta el FPGA al backplane del chasis y típicamente proporciona FPGA Mezzanine Connectors (FMC) para conectar placas con conversores analógico-digitales (ADC). Un ADC conectado a través de la interfaz FMC muestrea las señales analógicas pasadas a los núcleos de procesamiento OpenCL. Utilizando OpenCL, los núcleos FPGA se comunican con la máquina anfitriona de una manera estandarizada. Para demostrar la aplicabilidad de esta metodología, se seleccionaron e implementaron problemas de referencia de la literatura, tanto con soluciones tradicionales como de Deep Learning (DL). La metodología elabora ejemplos de conexión de núcleos OpenCL para cualquier caso de uso, y los resultados muestran ejemplos de conjuntos de núcleos. El problema de medición del flujo de neutrones se resuelve a 1GS/s en tiempo real utilizando técnicas de conteo de pulsos y Campbell, utilizando el 40% del objetivo FPGA Arria10. El ejemplo de aplicación DL se basa en una red neuronal para la discriminación neutrones/gammas que logra una tasa de clasificación de hasta 1.3 MEventos/s utilizando menos del 25% de la FPGA objetivo. LABURPENA Ezagutza zientifikoa aurreratzen duten makinak eraikitzea gure garaiko erronka garrantzitsuenetako bat da. Big Science deritzonaren makinak bakarrak dira; beharrezko esperientzia diziplina anitzekoa da, eta herrialde gutxik eraiki eta mantendu ditzakete. Baliabideak eta aurrekontuak mugagabeak ez direnez, konponbide eraginkorrak behar dira. Zientzia Handi makinak hamarkada bat behar dute diseinatuak izateko, hamarkada bat eraikitzeko eta gutxienez hamarkada bat jarduteko. Makina horietako bat fusio-erreaktore handienaren proiektua da, ITER, fusio-ikerketan hurrengo urratsa izango dena eta sistemak integratzeko erronka handia aurkezten duena. Integrazio-ahalegina arintzeko, ITERek estandarizazioan inbertitu du, bai softwarean bai - eta EPICS helburu orokorreko kontrol-sistema banatua. Kontrol-sistema horiek funtsezkoak dira instalazioa kudeatzeko. Komunikazio-protokoloak, prozesuen kudeaketa, monitorizazioa, alarmak eta pertsona-makina interfazeak bezalako funtzioak ematen dituzte, datubaseetarako edo datuak eskuratzeko sistemetarako sarbide aurreratua izateaz gain. Azken hori "Field Programmable Gate Array" (FPGA) batek kudeatzen du, milaka FPGA konektatuz makina bakoitzean eta kontrol-sistemaz milioika seinale kudeatuz. FPGA duten datuak eskuratzeko sistemek (DAQ) programazio aditua eta neketsua eskatzen jarraitzen dute. Problema hori ebazteko marko estandarizatuak, modularrak eta kode irekikoak proposatu dira, hala ere, FPGA hardware programazio espezializatuaren beharra ezin izan da ukatu. Tesi honek DAQ sistema hauek kontrol sistematik hardwareraino kontsideratuz teknologia bilduma bat programazio-ahalegina murrizten du. FPGA gailuak C/C++ antzeko inguruneak erabiliz programatzen dira, - OpenCL izenekoa, C++n idatzita dago, ITERren "Nominal Device Support v3" (NDSv3) eredua jarraituz. Honek software-gailuen garapena diseinu abstraktu eta orokorrez EPICSekiko interfazea sinplifikatzen du. IRIOOpenCL berariaz diseinatuta dago instrumentazio-sistema adimendunen integrazioa sinplifikatzeko, eta algoritmoak FPGAn integratzea ahalbidetzen du, software zati handiak aldatu gabe. Modularitateari eusteko, MTCA estandarra aukeratu da. Txasisaren backplanea Ethernet eta PCIe bidez konektatzen da gailuetara, komunikazio estandarrak gaituz. "Advanced Mezzanine Card" MTCAren ohiko DAQ FPGA plaka eramailea da. FPGA txasisaren backplanera konektatzen du eta, normalean, "FPGA Mezzanine Connectors"ak (FMC) ditu plaka bihurgailu analogiko-digitalak (ADC) konektatzeko. ADCak, FMC interfazearen bidez konektatuta, OpenCL prozesatze-nukleoetara igarotako seinale analogikoak bihurtzen ditu. OpenCL erabiliz, FPGA nukleoak ordenagailuarekin modu estandarizatuan komunikatzen dira. Metodologia horren aplikagarritasuna egiaztatzeko, erreferentziazko adibideak literaturatik hautatu eta nukleoen konexio-adibideak egiten ditu, edozein kasutan erabiltzeko, eta emaitzek nukleo multzoen adibideak erakusten dituzte. Neutroi-fluxuaren neurketak 1GS/s-ko ebazten dira real time errendimenduaz, pultsuak eta Campbell zenbatzeko teknikak erabiliz, Arria10 FPGAren % 40 erabiliz. Azkenik, DL aplikazioaren adibidea, neutroi/gamma sailkapena, sare neuronal batean oinarritzen da, eta FPGAren baliabideen % 25 baino gutxiago erabiliz 1.3 MSailkapen/s sailkapen-tasa lortzen du.

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field-programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

Real-time simulation of distribution system is challenging due to its' complex structure consisting of DGs. In this literature, a real-time simulator for distribution system with DG integration based on the field programmable gate array (FPGA) is realized for hardware emulation. The overall framework and asynchronous multi-rate interface method between DG with high nonlinearity and distribution system is proposed. The models of main components in distribution system are designed in FPGA. The hardware parallelism and highly pipeline design is utilized to guarantee real-time simulation, which has strong generality and flexibility. The simulator uses a floating point arithmetic calculation to achieve high accuracy. To validate the new simulator, a photovoltaic-battery hybrid generation system and a typical distribution system integrated with PV generation system are emulated in the hardware. The time-step of DG system and distribution system reach 1.096μs/1.696μs and 2μs/2μs respectively. The captured waveforms show excellent accuracy in comparison to the offline simulation in PSCAD/EMTDC. The time-step is less than RTDS which indicate a higher precision. The resource consumption of FPGA also show advantage compared with RTDS.

The method for modeling switching converters plays a key role in real-time simulators. Associate discrete circuit (ADC) modeling technique is a commonly used method for modeling the switching converter. However, the optimal selection of the ADC-based switch model parameters has great importance in the accuracy of the real-time simulator. In this paper, the design of a real-time simulator for a switching power converter has been done, in which a novel method for detecting optimum values of the switch model parameters has been expressed. Particle swarm optimization (PSO) algorithm is used to find these optimum values using state-space analysis of the modeled circuit in the z-domain. The modified nodal analysis (MNA) method solves the real-time model at each simulation time-step. Case studies are a single-phase 5-level Cascaded H-Bridge (CHB), three-phase 9-level CHB inverter, and a Transmission line. Field-programmable gate array (FPGA) has been used as a platform for implementing the real-time simulator. Experimental result of the real-time simulator of the 5-level CHB inverter on a SPARTAN-6 FPGA and its comparison with the result of a prototype of a 5-level CHB inverter confirms not only the performance of the real-time simulator, but also the effectiveness of the proposed method for confirming the real-time simulator accuracy.

The implementation of face recognition techniques in an embedded system is a very important aspect of various security applications, such as authorization identification in cash machines and door access for employee attendance. The purpose of this paper is to survey the existing hardware implementations of a face recognition system, particularly those who used for developing an embedded door access control system. This includes a brief discussion about face recognition algorithms and the hardware platforms outlining the importance of using a Field Programmable Gate Array (FPGA) device, which can be used to design an embedded door access control system. It is found that the success of any door access control system depends on the type of face recognition algorithm in the feature extraction phase of the face recognition system and the selected hardware device. Based on a comparison between different feature extraction algorithms, the use of a hybrid feature extraction technique can improve the accuracy of face recognition system. An efficient door access control system can be obtained using a FPGA device, which is preferable because of its technical characteristics of parallelism, re-programmability and very high speed, in the implementation of a face recognition system.

The field-programmable gate array (FPGA)-based real-time simulator takes advantage of many merits of FPGA, such as small time-step, high simulation precision, rich I/O interface resources, and low cost. The sparse linear equations formed by the node conductance matrix need to be solved repeatedly within each time-step, which introduces great challenges to the performance of the real-time simulator. In this paper, a fine-grained solver of the FPGA-based real-time simulator for active distribution networks is designed to meet the computational demand. The framework of the solver, offline process design on PC and online process design on FPGA are proposed in detail. The modified IEEE 33-node system with photovoltaics is simulated on a 4-FPGA-based real-time simulator. Simulation results are compared with PSCAD/EMTDC under the same conditions to validate the solver design.

The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the internal FPGA by implementing scrubbing strategy and thus improve the reliability of the whole system.

This paper presents the implementation and experimental details of a real-time digital simulator designed for representing a Distribution Static Compensator (D-STATCOM) interfaced with a digital controller. Real-time simulation using conventional fixed time-step integration algorithms can lead to erroneous results due to the lack of synchronism between the simulator time-step and the discrete switching signals coming from the digital controller. The real-time simulation algorithm implemented in this paper overcomes the drawbacks of a fixed time-step algorithm. The real-time algorithm relies on precise registration of timing of the incoming discrete firing pulses and a subsequent correction procedure to calculate the system state. This approach has been implemented on a hybrid digital processing platform comprising of a Digital Signal Processor (DSP) and a Field Programmable Gate Array (FPGA). The platform represents both the power electronic system and the digital control system. Experimental results, for a 5 kV A D-STATCOM system, in verification of the real-time simulator results are also provided.

This paper presents a field-programmable gate array (FPGA)-based real-time digital simulator for power electronic apparatus based on a realistic device-level behavioral model. A three-level 12-pulse voltage source converter (VSC)-fed induction machine drive is implemented on the FPGA. The VSC model is computed at a fixed time step of 12.5 ns, allowing a realistic representation of insulated-gate bipolar transistor (IGBT) nonlinear switching characteristics and power losses. The simulator also models a squirrel-cage induction machine, a direct field-oriented control system, and a pulsewidth modulator to achieve the real-time simulation of the complete drive system. All the models have been implemented using very high speed integrated circuit hardware description language (VHDL). Real-time simulation results have been validated using the measured device-level IGBT characteristics.

The microgrid containing a large amount of high frequency power switches and nonlinear components has put forward high requirements for power system real-time simulation technology. Multivalued coefficient prestorage can reduce the calculation steps in real-time simulation. In order to reduce the storage pressure of the multivalued coefficients, the whole network is divided into multiple subnetworks that can be simulated in parallel, and only the parameters for computing input variables and internal variables are prestored. The multiport hybrid equivalent is performed to reduce the number of simultaneous network equations. The input variables are tied to state variables of the circuit so that the iterative calculation is limited to the local network. The devised methodology is validated through simulation of a low-voltage microgrid on a field programmable gate array (FPGA)-based real-time digital simulation (FRTDS) platform at a 5 μs time step. Comparison with a power systems computer aided design (PSCAD)/electromagnetic transients including DC (EMTDC) model shows that the proposed method is effective.