Design of an ultra high speed AES processor for next generation IT security

Advanced Encryption Standard (AES), which is approved and published by Federal Information Processing Standard (FIPS), is a cryptographic algorithm that can be used to protect electronic data. The AES algorithm can be programmed in software or hardware. This paper presents encryption time comparison of the AES algorithm on FPGA and computer. In the study, Verilog HDL and C programming language is used on the FPGA and computer, respectively. The AES algorithm with 128-bit input and key length 128-bit (AES-128) was simulated on Xilinx ISE Design Suite 13.3. It was observed that, the AES algorithm runs on the FPGA faster than on a computer. We measured the time of encryption on FPGA and computer. Encryption time is 390ns of AES on FPGA and 11 μs of AES on a computer.

This paper presents the evaluation of a multidimensional IT security measurement method. The underlying solution was developed for the target group of handicraft business as micro-enterprises, i.e. 1 to 9 persons in the context of German industry and IT security requirements. The study aims to test hypotheses. Furthermore, it is to be determined which staged IT security status the subject groups have and which differences arise after a second measurement. In the result of the study the status quo of the target group and an increase of the IT security by application of the results of the measuring instrument after the 1. measurement is to be seen.

Industry managers have long recognized the vital importance of information security for their businesses, but at the same time they perceived security as a technology-driven rather then a business-driven field. Today, this notion is changing and security management is shifting from technology- to business-oriented approaches. Whereas there is evidence of this shift in the literature, this paper argues that security standards and academic work have not yet taken it fully into account. We examine whether this disconnect has lead to a misalignment of IT security requirements in businesses versus industry standards and academic research. We conducted 13 interviews with practitioners from 9 different firms to investigate this question. The results present evidence for a significant gap between security requirements in industry standards and actually reported security vulnerabilities. We further find mismatches between the prioritization of security factors in businesses, standards and real-world threats. We conclude that security in companies serves the business need of protecting information availability to keep the business running at all times.

The Consultative Committee for Space Data Systems (CCSDS) recommends AES algorithm as a cryptographic algorithm to maintain confidentiality and data security between spacecraft and ground systems. In implementation, there are several AES algorithm operating modes including Cipher-Block Chaining (CBC), Electronic Codebook (EBC), Cipher Feedback (CFB), Output Feedback (OFB), and counter mode (CTR). One of the operating modes of AES algorithm recommended by CCSDS is CTR because it has advantages in terms of efficiency of implementation and offers a high level of data security. LAPAN-A4 as the next generation of LAPAN satellites also uses CCSDS standard in terms of data exchange between satellites and ground stations including telemetry and telecommand (TTC) data and satellite payload data. In order to protect LAPAN-A4 satellite data, especially TTC data, in this paper AES algorithm was implemented in CTR operating mode on the FPGA which will then be implemented on LAPAN-A4 satellite onboard data handling (OBDH) as one of LAPAN-A4 satellite data security systems. To overcome the limited resource of FPGA, optimization is also done using basic iterative AES hardware reused method, which is to reuse hardware that has been designed n times for same operation for AES algorithm. From the results of implementation and optimization, efficiency of logic gates used is increasing almost a quarter less than the previous research.

While many organizations offer certifications associated with information technology (IT) security, there is no single overarching accrediting organization that has identified the body of knowledge and experience necessary for success in the IT security field. In order for an IT security workforce to be acknowledged and recognized throughout the world as possessing a proven level of education, knowledge, and experience in IT security, a formal process for certifying IT security professionals must be developed. This research effort suggests that the IT security community use the Project Management Institute’s process for certifying Project Management Professionals (PMPs) as a model for developing an open and easily accessible IT Security Body Of Knowledge (ITSBOK) and an associated international certification process for IT security professionals.

This study discusses the effectiveness of using AES (Advanced Encryption Standard) and RC4 (Rivest Chipper 4) as digital data security algorithms to prevent and protect transaction data from irresponsible parties. This needs to be done because the development of sales transactions or other services has used digital technology a lot. This situation causes the need to secure digital data from existing transactions, so that transaction data can be stored safely. Transaction data security is carried out by changing data into ciphers or codes that are difficult to read using the AES (Advanced Encryption Standard) and RC4 (Rivest Cipher 4) algorithms. This research begins by collecting existing transaction data and then transforming it into ASCII code. The results of the transformation will be used to perform calculations using the AES algorithm. After completing the calculation process using the AES algorithm, then do the calculations using RC4. These results will be stored in the database so that the transaction data that has turned into these codes cannot be known by other parties. The combination of the AES and RC4 algorithms is carried out to strengthen data encryption because there are more and more rotation systems and double security is carried out so that digital data is not easily read and misused. With the presence of this research, it can be shown that the AES and RC4 algorithms are capable of encrypting existing transaction data with multiple levels of security.

As the digital retail landscape is rapidly evolving, retailers find themselves to be poorly equipped to handle increasingly sophisticated cyber threats. In the past, retailers gave little importance to IT security. IT security requirements were narrowly framed as ‘checkbox compliance’ given by payment card industry (PCI) for data protection specification and outsourced implementation to individual stores. As the consumer habits are changing, security also should be given a redefined focus. Compliance and privacy requirements are making data protection a very essential and critical task. The paper addresses gaps and solutions for cyber security in retail domain, especially in the backdrop of digitalization and omnichannel retailing.

Legally supervised measuring instruments, like supermarket scales or utility meters for the supply of electricity, to name just a few, need to be checked in most countries. In this regard, smart meters are a fitting example for distributed systems that need to fulfill many IT security requirements. It is of utterly importance to make sure that the functionality of these measuring devices is preserved, with the goal to enhance trust in the market, protect the consumer of fraud, and preserve privacy. Normally, legally controlled measuring devices are checked before commissioning by so-called Notified Bodies, and afterwards cyclically by market surveillance officers. The hardware is scrutinized by manually testing the sensors. This paper looks more closely at the software testing aspect and highlights how current methods can be enhanced to check correct software functionality. We describe alternatives that will pave the way to a more secure and trustworthy market, which additionally, grants more flexibility to patch software bugs without the need for recertification, as long as the core functionality of the device remains the same. In our framework the functionality checking can be done automatically, while preserving confidentiality on all ends. Based on this framework, it is no problem to allow remote displays, e.g., smartphones, or, a completely distributed measuring instrument, e.g., with many sensors in different locations connected over the Internet. Our approach is of general nature, but perhaps most interesting for smart meter infrastructures.

The meaning of security is to protect something important from not authorized peoples. Cryptography is one of the security systems. Many applications could be used in the security systems like military applications, email, banking, information technology of database. The proposed system uses advanced encryption standard(AES) with secure hash algorithms(SHA-1) to produce a strong ciphertext. Moreover, this paper make the combination of (SHA-1) which is a one way encryption, as a key with (AES) algorithm which is a two way encryption as a ciphering generator to obtain confidentiality and integrity, In this paper presented implementation of Advanced Encryption Standard (AES) and Secure Hash (SHA-1) Algorithm by the use of FPGA Hardware card, However implementation of the AES algorithm and SHA-1 using LABVIEW environment with MATLAB system generator to generate stream data to FPGA hardware target. The output of the hash function is used as an input key for AES in order to improve data security, From the algorithms result of AES and SHA-1 obtained in FPGA, the system obtained how it is simple in modeling hashing and AES algorithms, generating hash codes and plain texts in (small and capital letters), symbols and numbers. The FPGA card used in this system (Spartan 3AN)with frequency (50%), the complete system take (1,147)size from the available space of (11,776) and accuracy (90%),the system work properly.

- The Advanced Encryption Standard (AES) is a widely used symmetric key encryption algorithm that secures digital data in modern communication systems. Conventional AES hardware implementations often consume high power, limiting their efficiency in resource-constrained environments. This paper presents a low-power AES hardware design implemented in Verilog HDL. The base design uses AES-128 with a 128-bit data block and 128-bit key, while the proposed design enhances security with a 256- bit key. Flip-flop based clock gating is applied to reduce dynamic power by minimizing unnecessary switching activity. Simulation results demonstrate that the proposed architecture effectively reduces power consumption while maintaining encryption performance, making it suitable for applications in IoT devices, embedded systems, and other low-power environments. Key Words: Advanced Encryption Standard (AES), Verilog HDL, Clock Gating, Low-Power Design, Cryptographic Hardware, Power Optimization, AES-128, AES-256.

In this era of consumer electronics, cyber security is one of the key challenges. Any security, privacy, or protection methods that are deployed rely on cryptography. Advance encryption standard (AES) is one of the heavily used cryptography algorithms for its advantages. This chapter is dedicated to the process of AES and its hardware design in the form of IP core. Several hardware security techniques rely on AES IP core as an important block. Additionally, since this is such an important core, its self-protection against forgery/piracy is also crucial. Thus, this chapter will also discuss about AES IP core protection using watermarking.

The National Institute of Standards and Technology (NIST) of US announced Rijndael algorithm as the advanced encryption standard (AES) in October 2000, Despite AES surpassing in security the data encryption standard (DES), it is still rare to be implemented in smart cards, due to the reason of deficient AES coprocessors. Here a chip operation system (COS) called NexCard, which derived from Microsoft's Windows COS, is used as the AES implementation platform. After a suitable COS architecture design for AES and methodology of efficient memory usage, the simulation result shows that direct embedding AES encryption attains 0.56 ms at system clock 15 MHz on the INFINEON SLE66CX322P chip without existence of coprocessor. Corresponding to the development needs in smart card cryptographic algorithm implementations, and different level of the security design specifications, a concept to conjoin numbers of algorithms into single smart card called cipher system on demand (CSOD) method is accomplished in this study concurrently. This is a method utilizing the multiapplication capability of NexCard v2.0 to execute the same AES algorithm as an on-card applet. Although the performance of CSOD is not as good as AES embedded method, CSOD can provide the same result in the situation of adaptability and extendibility.

Chapter 9 - Corporate IT Security Project Plan

File-sharing activities become a bridge for communication in the form of data between one party and another party. File sharing allows users to share data with other users, by uploading data to the server computer and other users can download data from the server computer. A document security system is indispensable to keep document data safe until its destination. File Web Sharing will transmit data with cryptographic methodologies. The algorithm used is Advanced Encryption Standard (AES), Data Encryption Standard (DES), and Blowfish. This study aims to compare the performance of AES, DES, and Blowfish algorithms when implemented to secure file sharing. Performance research results show that the DES algorithm is on average 8.35% faster than AES and the Blowfish algorithm is 7.11% faster than AES. Memory usage capacity testing shows that the AES algorithm requires 4.82% greater memory capacity than Blowfish, and the DES requires 2.41% greater memory capacity than the Blowfish algorithm. Kegiatan file sharing menjadi jembatan komunikasi data antara satu pihak dengan pihak lainnya. File sharing memberikan pengguna kemampuan untuk berbagi data dengan pengguna lain, dengan cara mengunggah data ke komputer server dan pengguna lain dapat mengunduh data dari komputer server. Sistem keamanan terhadap dokumen sangat diperlukan untuk menjaga data dokumen tetap aman sampai tujuannya. Web File Sharing akan mengirimkan data dengan metodologi kriptografi. Algoritma yang digunakan adalah Advanced Encryption Standard (AES), Data Encryption Standard (DES), dan Blowfish. Penelitian ini bertujuan untuk membandingkan kinerja algoritma AES, DES dan Blowfish saat diimplementasikan untuk mengamankan file sharing. Hasil pengujian kinerja menunjukkan bahwa algoritma DES rata-rata 8,35% lebih cepat dibandingkan AES sedangkan Blowfish 7,11% lebih cepat dibandingkan AES. Berdasarkan pengujian kapasitas penggunaan memori terlihat bahwa AES membutuhkan kapasitas memori 4,82% lebih besar dibandingkan Blowfish dan DES membutuhkan kapasitas memori 2,41% lebih besar dari Blowfish.

Encryption and decryption of data with very low latency and high energy efficiency is desirable in almost every application that deals with sensitive data. The advanced encryption standard (AES) is a widely adopted algorithm in symmetric key cryptography with numerous efficient implementations. Nonetheless, in scenarios involving extensive data processing, the primary limitations on performance and efficiency arise from data movement between memory and the processor, rather than data processing itself. In this article, we present a novel in-memory computing (IMC) approach for AES encryption and key-expansion, and experimentally validate it on an IMC prototype chip based on phase-change memory (PCM) technology. We leverage operators stored in PCM crossbar arrays to achieve the flexibility to tune performance at runtime based on the amount of free storage available in the memory system. In addition, we introduce a method for parallel in-memory polynomial modular multiplication and evaluate the potential of intrinsic stochastic properties of PCM devices for random key generation. We show how to further improve efficiency with minimal additional auxiliary circuitry. To evaluate the performance within a custom-built large-scale in-memory AES system, we design and implement a cycle-accurate simulator that integrates parameters from Spice simulations for detailed latency and energy consumption analysis of the AES algorithm. Our evaluations indicate that our IMC-based AES approach outperforms state-of-the-art methods, achieving speed factor improvements of up to 19.7 at equivalent energy efficiency.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.